Inventor · disambiguated record
Susan K. Lichtensteiger
Also filed as: LICHTENSTEIGER SUSAN K
32 granted patents·2 pending applications·305 citations·filing 1990–2018
97Inventor score
Top patents by PatentIndex Score
34 records- 0195US7475366B2Integrated circuit design closure method for selective voltage binningIBM·Filed 2006·Granted Jan 6, 2009·53 cites·14 claims
- 0293US8543960B1Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperaturesBICKFORD JEANNE P·Filed 2012·Granted Sep 24, 2013·10 cites·16 claims
- 0392US9269407B1System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over timeIBM·Filed 2015·Granted Feb 23, 2016·14 cites·20 claims
- 0489US8421495B1Speed binning for dynamic and adaptive power controlANEMIKOS THEODOROS E·Filed 2011·Granted Apr 16, 2013·11 cites·24 claims
- 0589US6792582B1Concurrent logical and physical construction of voltage islands for mixed supply voltage designsIBM·Filed 2000·Granted Sep 14, 2004·65 cites·61 claims
- 0688US9619609B1Integrated circuit chip design methods and systems using process window-aware timing analysisGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 11, 2017·6 cites·20 claims
- 0787US8141012B2Timing closure on multiple selective corners in a single statistical timing runBUCK NATHAN C·Filed 2009·Granted Mar 20, 2012·18 cites·22 claims
- 0885US7917451B2Methods, apparatus, and program products to optimize semiconductor product yield prediction for performance and leakage screensIBM·Filed 2008·Granted Mar 29, 2011·10 cites·20 claims
- 0984US9772374B2Selective voltage binning leakage screenIBM·Filed 2012·Granted Sep 26, 2017·6 cites·20 claims
- 1083US9552447B2Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scalingGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 24, 2017·4 cites·19 claims
- 1181US10067184B2Product performance test binningANEMIKOS THEODOROS·Filed 2011·Granted Sep 4, 2018·4 cites·22 claims
- 1281US7810054B2Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut pointIBM·Filed 2008·Granted Oct 5, 2010·11 cites·6 claims
- 1380US9152168B2Systems and methods for system power estimationBICKFORD JEANNE P·Filed 2012·Granted Oct 6, 2015·9 cites·14 claims
- 1478US8020138B2Voltage island performance/leakage screen monitor for IP characterizationIBM·Filed 2008·Granted Sep 13, 2011·9 cites·8 claims
- 1578US7877714B2System and method to optimize semiconductor power by integration of physical design timing and product performance measurementsIBM·Filed 2008·Granted Jan 25, 2011·10 cites·7 claims
- 1677US7793239B2Method and system of modeling leakageIBM·Filed 2006·Granted Sep 7, 2010·12 cites·3 claims
- 1776US8086832B2Structure for dynamically adjusting pipelined data paths for improved power managementLICHTENSTEIGER SUSAN K·Filed 2007·Granted Dec 27, 2011·7 cites·9 claims
- 1874US8086988B2Chip design and fabrication method optimized for profitBUCK NATHAN·Filed 2009·Granted Dec 27, 2011·7 cites·25 claims
- 1973US8839165B2Power/performance optimization through continuously variable temperature-based voltage controlIBM·Filed 2013·Granted Sep 16, 2014·3 cites·20 claims
- 2071US6990645B2Method for static timing verification of integrated circuits having voltage islandsIBM·Filed 2003·Granted Jan 24, 2006·18 cites·30 claims
- 2170US8839170B2Power/performance optimization through temperature/voltage controlBICKFORD JEANNE P·Filed 2013·Granted Sep 16, 2014·2 cites·24 claims
- 2266US9865486B2Timing/power risk optimized selective voltage binning using non-linear voltage slopeGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 9, 2018·1 cites·15 claims
- 2362US10794952B2Product performance test binningIBM·Filed 2018·Granted Oct 6, 2020·0 cites·18 claims
- 2462US8499140B2Dynamically adjusting pipelined data paths for improved power managementLICHTENSTEIGER SUSAN K·Filed 2011·Granted Jul 30, 2013·1 cites·14 claims
- 2559US8963620B2Controlling circuit voltage and frequency based upon location-dependent temperatureIBM·Filed 2013·Granted Feb 24, 2015·1 cites·9 claims
- 2659US7821294B2Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional blockIBM·Filed 2008·Granted Oct 26, 2010·3 cites·13 claims
- 2758US6924661B2Power switch circuit sizing techniqueIBM·Filed 2003·Granted Aug 2, 2005·8 cites·36 claims
- 2857US10295592B2Pre-test power-optimized bin reassignment following selective voltage binningGLOBALFOUNDRIES INC·Filed 2017·Granted May 21, 2019·0 cites·17 claims
- 2957US8239791B2Method of designing multi-state restore circuitry for restoring state to a power managed functional blockLICHTENSTEIGER SUSAN K·Filed 2008·Granted Aug 7, 2012·1 cites·20 claims
- 3054US8843874B2Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperaturesIBM·Filed 2013·Granted Sep 23, 2014·0 cites·19 claims
- 3152US9759767B2Pre-test power-optimized bin reassignment following selective voltage binningGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 12, 2017·0 cites·11 claims
- 3244US2007271449A1System and method for dynamically adjusting pipelined data paths for improved power managementIBM·Filed 2006·Application pending·0 cites
- 3343US2014249782A1Dynamic power prediction with pin attribute data modelIBM·Filed 2013·Application pending·0 cites
- 3423US5046413AMethod and apparatus for band printing with automatic home compensationIBM·Filed 1990·Granted Sep 10, 1991·1 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →