Inventor · disambiguated record
Mark W. Kuemerle
Also filed as: KUEMERLE MARK W · KUEMERLE MARK WILLIAM
26 granted patents·4 pending applications·198 citations·filing 1999–2025
95Inventor score
Top patents by PatentIndex Score
30 records- 0197US10748852B1Multi-chip module (MCM) with chip-to-chip connection redundancy and methodMARVELL INT LTD·Filed 2019·Granted Aug 18, 2020·20 cites·20 claims
- 0295US7475366B2Integrated circuit design closure method for selective voltage binningIBM·Filed 2006·Granted Jan 6, 2009·53 cites·14 claims
- 0393US8543960B1Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperaturesBICKFORD JEANNE P·Filed 2012·Granted Sep 24, 2013·10 cites·16 claims
- 0492US9269407B1System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over timeIBM·Filed 2015·Granted Feb 23, 2016·14 cites·20 claims
- 0588US9619609B1Integrated circuit chip design methods and systems using process window-aware timing analysisGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 11, 2017·6 cites·20 claims
- 0684US9501607B1Composite views for IP blocks in ASIC designsIBM·Filed 2015·Granted Nov 22, 2016·4 cites·20 claims
- 0783US9552447B2Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scalingGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 24, 2017·4 cites·19 claims
- 0880US11282806B2Partitioned substrates with interconnect bridgeMARVELL ASIA PTE LTD·Filed 2019·Granted Mar 22, 2022·3 cites·22 claims
- 0975US6457131B2System and method for power optimization in parallel unitsIBM·Filed 2001·Granted Sep 24, 2002·24 cites·24 claims
- 1073US8839165B2Power/performance optimization through continuously variable temperature-based voltage controlIBM·Filed 2013·Granted Sep 16, 2014·3 cites·20 claims
- 1172US10714411B2Interconnected integrated circuit (IC) chip structure and packaging and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·2 cites·19 claims
- 1272US9875956B1Integrated interface structureGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 23, 2018·2 cites·20 claims
- 1370US8839170B2Power/performance optimization through temperature/voltage controlBICKFORD JEANNE P·Filed 2013·Granted Sep 16, 2014·2 cites·24 claims
- 1469US9870163B2Double bandwidth algorithmic memory arrayGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 16, 2018·1 cites·20 claims
- 1569US8189723B2Method, circuit, and design structure for capturing data across a pseudo-synchronous interfaceBERHANU MALEDE W·Filed 2008·Granted May 29, 2012·8 cites·15 claims
- 1668US2024405795A1Lateral escape using triangular structure of transceiversMARVELL ASIA PTE LTD·Filed 2024·Application pending·0 cites
- 1766US9865486B2Timing/power risk optimized selective voltage binning using non-linear voltage slopeGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 9, 2018·1 cites·15 claims
- 1866US7529962B1System for expanding a window of valid dataIBM·Filed 2008·Granted May 5, 2009·3 cites·1 claims
- 1964US12095494B1Lateral escape using triangular structure of transceiversMARVELL ASIA PTE LTD·Filed 2022·Granted Sep 17, 2024·0 cites·20 claims
- 2064US9171125B2Limiting skew between different device types to meet performance requirements of an integrated circuitIBM·Filed 2014·Granted Oct 27, 2015·1 cites·20 claims
- 2159US8963620B2Controlling circuit voltage and frequency based upon location-dependent temperatureIBM·Filed 2013·Granted Feb 24, 2015·1 cites·9 claims
- 2259US6289465B1System and method for power optimization in parallel unitsIBM·Filed 1999·Granted Sep 11, 2001·36 cites·6 claims
- 2354US8843874B2Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperaturesIBM·Filed 2013·Granted Sep 23, 2014·0 cites·19 claims
- 2450US9372520B2Reverse performance binningGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 21, 2016·0 cites·18 claims
- 2550US2024258272A1Integrated circuit device with stacked interface chipletsMARVELL ASIA PTE LTD·Filed 2024·Application pending·0 cites
- 2646US11037873B2Hermetic barrier for semiconductor deviceAvera Semiconductor LLC·Filed 2019·Granted Jun 15, 2021·0 cites·19 claims
- 2746US10381304B2Interconnect structureGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 13, 2019·0 cites·20 claims
- 2846US2025316666A1Hybrid-bonded interposer for high-density interface connections in semconductor devicesMARVELL ASIA PTE LTD·Filed 2025·Application pending·0 cites
- 2945US2015025857A1Statistical power estimationIBM·Filed 2013·Application pending·0 cites
- 3044US8300752B2Method, circuit, and design structure for capturing data across a pseudo-synchronous interfaceBERHANU MALEDE W·Filed 2008·Granted Oct 30, 2012·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →