Inventor · disambiguated record
Srihari Makineni
Also filed as: MAKINENI SRIHARI
26 granted patents·16 pending applications·164 citations·filing 2002–2023
95Inventor score
Top patents by PatentIndex Score
42 records- 0192US7725657B2Dynamic quality of service (QoS) for a shared cacheINTEL CORP·Filed 2007·Granted May 25, 2010·33 cites·17 claims
- 0289US8036246B2Packet coalescingINTEL CORP·Filed 2009·Granted Oct 11, 2011·12 cites·4 claims
- 0387US7596662B2Selective storage of data in levels of a cache memoryINTEL CORP·Filed 2006·Granted Sep 29, 2009·21 cites·22 claims
- 0487US7552288B2Selectively inclusive cache architectureINTEL CORP·Filed 2006·Granted Jun 23, 2009·19 cites·14 claims
- 0584US7895415B2Cache sharing based thread controlINTEL CORP·Filed 2007·Granted Feb 22, 2011·16 cites·6 claims
- 0683US10652147B2Packet coalescingINTEL CORP·Filed 2017·Granted May 12, 2020·2 cites·21 claims
- 0783US8718096B2Packet coalescingMAKINENI SRIHARI·Filed 2010·Granted May 6, 2014·7 cites·12 claims
- 0882US7490191B2Sharing information between guests in a virtual machine environmentINTEL CORP·Filed 2006·Granted Feb 10, 2009·11 cites·20 claims
- 0981US9047171B2Differentiating cache reliability to reduce minimum on-die voltageINTEL CORP·Filed 2012·Granted Jun 2, 2015·7 cites·23 claims
- 1078US7620071B2Packet coalescingINTEL CORP·Filed 2004·Granted Nov 17, 2009·17 cites·17 claims
- 1177US10664039B2Power efficient processor architectureINTEL CORP·Filed 2018·Granted May 26, 2020·1 cites·7 claims
- 1277US9360927B2Power efficient processor architectureHERDRICH ANDREW J·Filed 2011·Granted Jun 7, 2016·4 cites·17 claims
- 1373US9870047B2Power efficient processor architectureINTEL CORP·Filed 2016·Granted Jan 16, 2018·1 cites·12 claims
- 1473US9864427B2Power efficient processor architectureINTEL CORP·Filed 2016·Granted Jan 9, 2018·1 cites·19 claims
- 1572US12248783B2Frequency scaling for per-core accelerator assignmentsINTEL CORP·Filed 2023·Granted Mar 11, 2025·0 cites·24 claims
- 1672US9395994B2Embedded branch prediction unitJIANG XIAOWEI·Filed 2011·Granted Jul 19, 2016·3 cites·24 claims
- 1769US9378164B2Interrupt return instruction with embedded interrupt service functionalityFANG ZHEN·Filed 2011·Granted Jun 28, 2016·2 cites·20 claims
- 1868US2020328973A1Packet coalescingINTEL CORP·Filed 2020·Application pending·0 cites
- 1961US11775298B2Frequency scaling for per-core accelerator assignmentsINTEL CORP·Filed 2020·Granted Oct 3, 2023·0 cites·22 claims
- 2059US8458711B2Quality of service implementation for platform resourcesILLIKKAL RAMESH G·Filed 2006·Granted Jun 4, 2013·3 cites·8 claims
- 2158US10048743B2Power efficient processor architectureINTEL CORP·Filed 2016·Granted Aug 14, 2018·0 cites·15 claims
- 2258US7525989B2System, method and device for time slot status messaging among SONET nodesINTEL CORP·Filed 2002·Granted Apr 28, 2009·4 cites·33 claims
- 2357US2017048142A1Packet coalescingINTEL CORP·Filed 2016·Application pending·0 cites
- 2455US11567556B2Platform slicing of central processing unit (CPU) resourcesINTEL CORP·Filed 2020·Granted Jan 31, 2023·0 cites·20 claims
- 2555US10095520B2Interrupt return instruction with embedded interrupt service functionalityINTEL CORP·Filed 2016·Granted Oct 9, 2018·0 cites·25 claims
- 2653US9753732B2Embedded branch prediction unitINTEL CORP·Filed 2016·Granted Sep 5, 2017·0 cites·17 claims
- 2750US12348969B2Systems, methods, and apparatus for workload optimized central processing units (CPUS)INTEL CORP·Filed 2021·Granted Jul 1, 2025·0 cites·21 claims
- 2845US9465751B2Efficient locking of memory pagesJIANG XIAOWEI·Filed 2012·Granted Oct 11, 2016·0 cites·18 claims
- 2945US2006072563A1Packet processingREGNIER GREG J·Filed 2004·Application pending·0 cites
- 3045US2012191896A1Circuitry to select, at least in part, at least one memoryFANG ZHEN·Filed 2011·Application pending·0 cites
- 3145US2006002705A1Decentralizing network management system tasksCLINE LINDA·Filed 2004·Application pending·0 cites
- 3243US2008244221A1Exposing system topology to the execution environmentNEWELL DONALD K·Filed 2007·Application pending·0 cites
- 3342US2006143245A1Low overhead mechanism for offloading copy operationsIYER RAVISHANKAR·Filed 2004·Application pending·0 cites
- 3442US2007130364A1Techniques to determine an integrity validation valueINTEL CORP·Filed 2005·Application pending·0 cites
- 3541US2004073717A1System method and device for dynamic mapping of sonet pathsFiled 2002·Application pending·0 cites
- 3641US2005246500A1Method, apparatus and system for an application-aware cache push agentIYER RAVISHANKAR·Filed 2004·Application pending·0 cites
- 3741US2004114640A1System, method and device for aggregating SONET linksFiled 2002·Application pending·0 cites
- 3841US2009165004A1Resource-aware application schedulingMOSES JAIDEEP·Filed 2007·Application pending·0 cites
- 3938US2007150658A1Pinning locks in shared cacheMOSES JAIDEEP·Filed 2005·Application pending·0 cites
- 4037US2014223145A1Configurable Reduced Instruction Set CoreINTEL CORP·Filed 2011·Application pending·0 cites
- 4134US2014082334A1Encoding to Increase Instruction Set DensityKING STEVEN R·Filed 2011·Application pending·0 cites
- 4232US2014258685A1Using Reduced Instruction Set CoresMAKINENI SRIHARI·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →