US2008244221A1PendingUtilityA1

Exposing system topology to the execution environment

43
Individually held — no corporate assignee on recordPriority: Mar 30, 2007Filed: Mar 30, 2007Published: Oct 2, 2008
Est. expiryMar 30, 2027(~0.7 yrs left)· nominal 20-yr term from priority
Inventors:Donald NewellJaideep MosesRavishankar IyerRameshkumar G. IllikkalSrihari Makineni
G06F 15/16
43
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Claims

Abstract

Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.

Claims

exact text as granted — not AI-modified
1 . An apparatus comprising;
 a plurality of execution cores on a single integrated circuit;   a plurality of resources on the single integrated circuit; and   topology logic to populate a data structure with information regarding at least one relationship between at least one of the plurality of execution cores and at least one of the resources.   
   
   
       2 . The apparatus of  claim 1 , wherein the plurality of resources includes cache memories. 
   
   
       3 . The apparatus of  claim 1 , wherein at least one of the resources is shared by at least two of the plurality of execution cores. 
   
   
       4 . The apparatus of  claim 1 , wherein at least one of the plurality of execution cores includes at least two hardware threads. 
   
   
       5 . The apparatus of  claim 1 , wherein the topology logic is to populate the data structure with information regarding the latency associated with each execution core accessing each resource. 
   
   
       6 . The apparatus of  claim 4 , wherein the topology logic is to populate the data structure with information regarding the latency associated with each hardware thread accessing each resource. 
   
   
       7 . The apparatus of  claim 3 , wherein the topology logic is to populate the data structure with information regarding the sharing of resources. 
   
   
       8 . The apparatus of  claim 1 , wherein at least one of the execution cores is to execute scheduling software to schedule processes to run on the plurality of execution cores. 
   
   
       9 . The apparatus of  claim 8 , wherein the scheduling software is to schedule the processes based on information stored in the data structure. 
   
   
       10 . A method comprising:
 storing information regarding relationships among a plurality of execution cores and a plurality of resources on a single integrated circuit; and   using the information to schedule processes to am on the plurality of execution cores.   
   
   
       11 . The method of  claim 10 , wherein the plurality of resources includes cache memories. 
   
   
       12 . The method of  claim 10 , wherein storing information includes storing information regarding the latency associated with each execution core accessing each resource. 
   
   
       13 . The method of  claim 10 , wherein storing information includes storing information regarding the sharing of the resources by the execution cores. 
   
   
       14 . A system comprising:
 a multicore processor including:
 a plurality of execution cores; 
 a plurality of resources; and 
 topology logic to populate a data structure with information regarding at least one relationship between at least one of the plurality of execution cores and at least one of the resources; and 
   a memory to store the data structure.   
   
   
       15 . The system of  claim 14 , further comprising firmware to be executed by one of the plurality of execution cores to build the data structure. 
   
   
       16 . The system of  claim 14 , wherein the memory is also to store a scheduling program to schedule processes to be executed by the system. 
   
   
       17 . The system of  claim 14 , wherein the scheduling program is to read information from the data structure to use in scheduling processing to be executed by the system. 
   
   
       18 . The system of  claim 14 , wherein the plurality of resources includes cache memories. 
   
   
       19 . The system of  claim 14 , wherein the topology logic is to store information regarding the latency associated with each execution core accessing each resource. 
   
   
       20 . The system of  claim 14 , wherein the topology logic is to store information regarding the sharing of the resources by the execution cores.

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