Inventor · disambiguated record
Mario Au
Also filed as: AU MARIO · AU MARIO F · AU MARIO FULAM
32 granted patents·2 pending applications·400 citations·filing 1996–2007
97Inventor score
Top patents by PatentIndex Score
34 records- 0191US7554379B2High-speed, low-power level shifter for mixed signal-level environmentsINTEGRATED DEVICE TECH·Filed 2007·Granted Jun 30, 2009·20 cites·7 claims
- 0287US6778454B2FIFO memory devices that support all combinations of DDR and SDR read and write modesINTEGRATED DEVICE TECH·Filed 2003·Granted Aug 17, 2004·39 cites·21 claims
- 0386US7042792B2Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arraysINTEGRATED DEVICE TECH·Filed 2004·Granted May 9, 2006·38 cites·8 claims
- 0485US7224195B2Output drive circuit that accommodates variable supply voltagesINTEGRATED DEVICE TECH·Filed 2004·Granted May 29, 2007·28 cites·8 claims
- 0584US6546461B1Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices thereinINTEGRATED DEVICE TECH·Filed 2000·Granted Apr 8, 2003·33 cites·35 claims
- 0683US6795360B2Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modesINTEGRATED DEVICE TECH·Filed 2001·Granted Sep 21, 2004·29 cites·56 claims
- 0774US7158440B2FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operationINTEGRATED DEVICE TECH·Filed 2004·Granted Jan 2, 2007·16 cites·10 claims
- 0874US5789953AClock signal generator providing non-integer frequency multiplicationINTEGRATED DEVICE TECH·Filed 1996·Granted Aug 4, 1998·32 cites·21 claims
- 0971US7257687B2Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Aug 14, 2007·5 cites·14 claims
- 1070US7392354B1Multi-queue FIFO memory devices that support a backed-off standard mode of operation and methods of operating sameINTEGRATED DEVICE TECH·Filed 2005·Granted Jun 24, 2008·4 cites·5 claims
- 1169US7082071B2Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modesINTEGRATED DEVICE TECH·Filed 2004·Granted Jul 25, 2006·16 cites·11 claims
- 1268US7870310B2Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Jan 11, 2011·4 cites·20 claims
- 1364US7246300B1Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generationINTEGRATED DEVICE TECH·Filed 2004·Granted Jul 17, 2007·10 cites·6 claims
- 1463US7805551B2Multi-function queue to support data offload, protocol translation and pass-through FIFOINTEGRATED DEVICE TECH·Filed 2007·Granted Sep 28, 2010·2 cites·23 claims
- 1563US6754777B1FIFO memory devices and methods of operating FIFO memory devices having multi-port cache memory devices thereinINTEGRATED DEVICE TECH·Filed 2002·Granted Jun 22, 2004·11 cites·8 claims
- 1662US7523232B2Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Apr 21, 2009·2 cites·16 claims
- 1762US7093047B2Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitrationINTEGRATED DEVICE TECH·Filed 2003·Granted Aug 15, 2006·12 cites·22 claims
- 1859US7076610B2FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating sameINTEGRATED DEVICE TECH·Filed 2003·Granted Jul 11, 2006·7 cites·5 claims
- 1958US7269700B2Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Sep 11, 2007·1 cites·3 claims
- 2058US7209983B2Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operationINTEGRATED DEVICE TECH·Filed 2003·Granted Apr 24, 2007·9 cites·12 claims
- 2158US7099231B2Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Aug 29, 2006·5 cites·11 claims
- 2257US6539465B2Method and apparatus for byte alignment operations for a memory device that stores an odd number of bytesINTEGRATED DEVICE TECH·Filed 2000·Granted Mar 25, 2003·4 cites·18 claims
- 2357US5867672ATriple-bus FIFO buffers that can be chained together to increase buffer depthINTEGRATED DEVICE TECH·Filed 1996·Granted Feb 2, 1999·37 cites·11 claims
- 2454US7586343B2Output drive circuit that accommodates variable supply voltagesINTEGRATED DEVICE TECH·Filed 2007·Granted Sep 8, 2009·2 cites·4 claims
- 2547US6122717AMethods and apparatus for a memory that supports a variable number of bytes per logical cell and a variable number of cellsINTEGRATED DEVICE TECH·Filed 1996·Granted Sep 19, 2000·15 cites·18 claims
- 2646US7945716B2Serial buffer supporting virtual queue to physical memory mappingINTEGRATED DEVICE TECH·Filed 2007·Granted May 17, 2011·1 cites·16 claims
- 2745US7805552B2Partial packet write and write data filtering in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Sep 28, 2010·0 cites·5 claims
- 2843US6243799B1Methods and apparatus for byte alignment operations for a memory device that stores an odd number of bytesINTEGRATED DEVICE TECH·Filed 1998·Granted Jun 5, 2001·11 cites·14 claims
- 2940US6874064B2FIFO memory devices having multi-port cache and extended capacity memory devices therein with retransmit capabilityINTEGRATED DEVICE TECH·Filed 2004·Granted Mar 29, 2005·2 cites·13 claims
- 3040US2006155940A1Multi-queue FIFO memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected FIFO memory chipsAU MARIO·Filed 2005·Application pending·0 cites
- 3134US7154327B2Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Dec 26, 2006·0 cites·17 claims
- 3234US6230249B1Methods and apparatus for providing logical cell available information in a memoryINTEGRATED DEVICE TECH·Filed 1998·Granted May 8, 2001·5 cites·14 claims
- 3332US8230174B2Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory systemAU MARIO·Filed 2005·Granted Jul 24, 2012·0 cites·17 claims
- 3431US2004047209A1FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating sameFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →