Multi-queue FIFO memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected FIFO memory chips

Abstract

Multi-Q FIFO memory systems include a plurality of multi-Q first-in first-out (FIFO) memory chips electrically coupled to a data output bus. The plurality of multi-Q FIFO memory chips, which are responsive to respective identification codes ID and respective read chip select signals (/RCS), are configured to support an enhanced multi-chip expansion mode of operation. This expansion mode of operation uses the read chip select signals to control one-at-a-time access of at least two selected multi-Q FIFO memory chips receiving equivalent ID codes and equivalent read addresses to the output data bus during read operations.

1 . An integrated circuit system, comprising: 
 an output data bus; and    a plurality of multi-Q first-in first-out (FIFO) memory chips electrically coupled to said data output bus, said plurality of multi-Q FIFO memory chips responsive to respective ID codes and respective read chip select signals and configured to support a multi-chip expansion mode of operation that uses the read chip select signals to control one-at-a-time access of at least two of said plurality of multi-Q FIFO memory chips receiving equivalent ID codes and equivalent read addresses to said output data bus during read operations.    
   
   
       2 . The system of  claim 1 , wherein said plurality of multi-Q FIFO memory chips are configured so that the read chip select signals dispose all but a selected one of said plurality of multi-Q FIFO memory chips in a high impedance output mode during a read operation.  
   
   
       3 . The system of  claim 2 , wherein said plurality of multi-Q FIFO memory chips are configured so that a most significant portion of a read address is compared to the ID codes associated with said plurality of multi-Q FIFO memory chips to detect an equivalency therebetween during a read operation.  
   
   
       4 . A method of operating a depth-expanded system of multi-Q FIFO memory chips coupled to a common data output bus, comprising the steps of: 
 comparing bits of an applied read address to applied ID codes associated with the multi-Q FIFO memory chips to thereby identify a plurality of the multi-Q FIFO memory chips as candidates to undergo a read operation; and    deselecting all but one of the candidate multi-Q FIFO memory chips using a plurality of read chip select signals to dispose data output ports of the deselected multi-Q FIFO memory chips in high impedance states.    
   
   
       5 . An integrated circuit device, comprising: 
 a multi-Q first-in first-out (FIFO) memory chip responsive to a multi-bit ID code, a multi-bit read address and a read chip select signal, said multi-Q FIFO memory chip configured to support a multi-chip expansion mode of operation that allows for multiple FIFO memory chips to receive equivalent ID codes and read addresses when assembled in a multi-chip FIFO system.