Inventor · disambiguated record
Steven M. Eustis
Also filed as: EUSTIS STEVEN M · EUSTIS STEVEN MICHAEL
16 granted patents·2 pending applications·113 citations·filing 1997–2008
92Inventor score
Top patents by PatentIndex Score
18 records- 0182US6928377B2Self-test architecture to implement data column redundancy in a RAMIBM·Filed 2003·Granted Aug 9, 2005·33 cites·15 claims
- 0276US6944075B1Variable column redundancy region boundaries in SRAMIBM·Filed 2005·Granted Sep 13, 2005·10 cites·20 claims
- 0369US7007214B2Diagnosable scan chainIBM·Filed 2003·Granted Feb 28, 2006·14 cites·29 claims
- 0461US6778419B2Complementary two transistor ROM cellIBM·Filed 2002·Granted Aug 17, 2004·11 cites·17 claims
- 0556US6721927B2Substituting high performance and low power macros in integrated circuit chipsIBM·Filed 2002·Granted Apr 13, 2004·7 cites·20 claims
- 0654US5920222ATunable pulse generator based on a wave pipelineIBM·Filed 1997·Granted Jul 6, 1999·13 cites·16 claims
- 0749US6570254B1Electrical mask identification of memory modulesIBM·Filed 2001·Granted May 27, 2003·2 cites·13 claims
- 0846US6600673B1Compilable writeable read only memory (ROM) built with register arraysIBM·Filed 2003·Granted Jul 29, 2003·5 cites·20 claims
- 0944US6038179AMultiple repair size redundancyIBM·Filed 1999·Granted Mar 14, 2000·11 cites·7 claims
- 1043US7404125B2Compilable memory structure and test methodology for both ASIC and foundry test environmentsIBM·Filed 2005·Granted Jul 22, 2008·1 cites·7 claims
- 1142US6922349B2Complementary two transistor ROM cellIBM·Filed 2004·Granted Jul 26, 2005·3 cites·6 claims
- 1239US7937632B2Design structure and apparatus for a robust embedded interfaceIBM·Filed 2008·Granted May 3, 2011·0 cites·15 claims
- 1339US7210085B2Method and apparatus for test and repair of marginally functional SRAM cellsIBM·Filed 2003·Granted Apr 24, 2007·3 cites·22 claims
- 1437US2008256405A1Compilable memory structure and test methodology for both asic and foundry test environmentsIBM·Filed 2008·Application pending·0 cites
- 1533US8239715B2Method and apparatus for a robust embedded interfaceEUSTIS STEVEN M·Filed 2008·Granted Aug 7, 2012·0 cites·20 claims
- 1630US6675273B2Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requestedIBM·Filed 2001·Granted Jan 6, 2004·0 cites·22 claims
- 1729US2003007393A1Method and apparatus for testing memory arraysIBM·Filed 2001·Application pending·0 cites
- 1827US6268228B1Electrical mask identification of memory modulesIBM·Filed 1999·Granted Jul 31, 2001·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →