Compilable memory structure and test methodology for both asic and foundry test environments

Abstract

A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.

1 . A method of implementing a compilable memory structure configured for supporting multiple test methodologies, the method comprising:
 configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith;   configuring a second multiplexer for selectively coupling an input of a test latch between a functional memory array connection and a memory logic test connection, said memory logic test connection coupled to said at least one data input path with an output of said test latch defining a data out customer connection; and   configuring flush logic to direct data from said memory logic connection to said data out customer connection during a test of logic associated with a customer chip, thereby facilitating observation of said memory logic connection at said customer chip;   wherein test elements of the memory structure comprise a scan architecture of a first type and test elements of said customer chip comprise a scan architecture of a second type.   
   
   
       2 . The method of  claim 1 , wherein said scan architecture of a first type further comprises a level sensitive scan design (LSSD), and scan architecture of a second type further comprises a muxed-flop design. 
   
   
       3 . The method of  claim 1 , further comprising configuring at least one external observation pin for said customer chip, said at least one external observation pin coupled to one or more of: said at least one address path of the memory structure, and a system clock path of the memory structure. 
   
   
       4 . The method of  claim 1 , further comprising:
 applying a first control signal to said first plurality of multiplexers, said first control signal comprising one of a first state and a second state;   said first state corresponding to one of: a functional mode of the memory structure, and a test mode of said logic associated with said customer chip; and   said second state corresponding to one of: a test mode of logic associated with the memory structure, and a built-in self test (BIST) and repair mode of the memory structure.   
   
   
       5 . The method of  claim 4 , further comprising:
 applying a second control signal to said second multiplexer, said second control signal comprising one of a first state and a second state;   said first state corresponding to one of: said functional mode of the memory structure, and said BIST and repair mode of the memory structure; and   said second state corresponding to one of: said test mode of said logic associated with said customer chip, and said test mode of logic associated with the memory structure.   
   
   
       6 . The method of  claim 5 , further comprising applying a flush logic control signal to said flush logic, wherein:
 said flush logic control signal is set to a first state in said functional mode of the memory structure;   said flush logic control signal is set to a second state in said test mode of said logic associated with said customer chip; and   said flush logic control signal is considered to be in a don't care state in said test mode of logic associated with the memory structure and in said BIST and repair mode of the memory structure.   
   
   
       7 . A method for implementing a plurality of test methodologies for a memory structure, the method comprising:
 setting a first test configuration in the memory structure in accordance with a first test methodology corresponding to a first scan architecture;   setting a second test configuration in the memory structure in accordance with a second test methodology corresponding to a second scan architecture; and   setting a third test configuration in the memory structure in accordance with a third test methodology corresponding to a built-in self test (BIST) and repair mode of the memory structure.   
   
   
       8 . The method of  claim 7 , wherein said setting a first test configuration in the memory structure further comprises:
 applying a first control signal so as to cause a first plurality of multiplexers to couple at least one data input path and at least one address path to a corresponding internal memory connection associated therewith;   applying a second control signal so as to cause a second multiplexer to couple an input of a test latch to a memory logic connection, said memory logic connection coupled to said at least one data input path, with an output of said test latch defining a data out customer connection.   
   
   
       9 . The method of  claim 8 , wherein said setting a second test configuration in the memory structure further comprises:
 applying said first control signal so as to cause said first plurality of multiplexers to couple said at least one data input path and said at least one address path to an external customer connection;   applying a second control signal so as to cause said second multiplexer to maintain said input of said test latch coupled to said memory logic connection; and   applying a flush logic signal so as to cause flush logic to direct data from said memory logic connection to said data out customer connection, thereby facilitating observation of said memory logic connection at said customer chip.   
   
   
       10 . The method of  claim 9 , further comprising configuring at least one external observation pin for said customer chip, said at least one external observation pin coupled to one or more of: said at least one address path of the memory structure, and a system clock path of the memory structure. 
   
   
       11 . The method of  claim 9 , wherein said setting a third test configuration in the memory structure further comprises:
 applying said first control signal so as to cause said first plurality of multiplexers to couple said at least one data input path and said at least one address path to said internal memory connection; and   applying said second control signal so as to cause said second multiplexer to couple said input of said test latch to a functional memory array connection.   
   
   
       12 . The method of  claim 9 , further comprising permitting said flush logic control signal to be in a don't care state in said first and said third test configurations. 
   
   
       13 . The method of  claim 7 , wherein said first scan architecture comprises a level sensitive scan design (LSSD), and said second scan architecture further comprises a muxed-flop design.