Inventor · disambiguated record
Kenneth J. Stern
Also filed as: STERN KENNETH · STERN KENNETH J · STERN KENNETH JEFFREY
14 granted patents·1 pending application·266 citations·filing 1987–2022
92Inventor score
Files withANALOG DEVICES INC7CRYSTAL SEMICONDUCTOR CORP3CRYSTAL SEMICONDUCTOR1IDEX ASA1IDEX BIOMETRICS ASA1
Top patents by PatentIndex Score
15 records- 0193US4941156ALinear jitter attenuatorCRYSTAL SEMICONDUCTOR·Filed 1989·Granted Jul 10, 1990·81 cites·21 claims
- 0286US6774694B1Timing vernier architecture for generating high speed, high accuracy timing edgesANALOG DEVICES INC·Filed 2002·Granted Aug 10, 2004·47 cites·29 claims
- 0380US4805198AClock multiplier/jitter attenuatorCRYSTAL SEMICONDUCTOR CORP·Filed 1987·Granted Feb 14, 1989·65 cites·14 claims
- 0476US10691258B2Systems and methods for noise reduction in sensorsIDEX ASA·Filed 2018·Granted Jun 23, 2020·2 cites·25 claims
- 0573US4988954ALow power output stage circuitry in an amplifierCRYSTAL SEMICONDUCTOR CORP·Filed 1989·Granted Jan 29, 1991·20 cites·19 claims
- 0666US7272526B2Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock periodANALOG DEVICES INC·Filed 2006·Granted Sep 18, 2007·6 cites·8 claims
- 0753US5150386AClock multiplier/jitter attenuatorCRYSTAL SEMICONDUCTOR CORP·Filed 1989·Granted Sep 22, 1992·19 cites·16 claims
- 0849US6242959B1Programmable delay circuit and method with dummy circuit compensationANALOG DEVICES INC·Filed 1999·Granted Jun 5, 2001·10 cites·36 claims
- 0945US6429712B1Precision set-reset logic circuit and methodANALOG DEVICES INC·Filed 2001·Granted Aug 6, 2002·3 cites·26 claims
- 1044US11914791B2Gesture control using biopotential-based analog front endPISON TECH INC·Filed 2022·Granted Feb 27, 2024·0 cites·20 claims
- 1142US11042773B2Systems and methods for accelerating data capture in sensorsIDEX BIOMETRICS ASA·Filed 2019·Granted Jun 22, 2021·0 cites·22 claims
- 1241US6326828B1Precision set-reset logic circuitANALOG DEVICES INC·Filed 1999·Granted Dec 4, 2001·6 cites·10 claims
- 1337US7050919B1Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock periodANALOG DEVICES INC·Filed 2003·Granted May 23, 2006·1 cites·12 claims
- 1437US6265901B1Fully differential logic or circuit for multiple non-overlapping inputsANALOG DEVICES INC·Filed 1999·Granted Jul 24, 2001·6 cites·15 claims
- 1536US2006184333A1Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock periodSTERN KENNETH·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →