US2006184333A1PendingUtilityA1
Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period
Est. expiryNov 19, 2023(expired)· nominal 20-yr term from priority
Inventors:Kenneth J. Stern
G01R 31/31922G01R 31/3191
36
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Claims
Abstract
A method of calibrating a timing vernier includes autocalibrating a plurality phase-delayed clock signal edges to match respective ideal signal edges, the phase-delayed clock signal edges dividing one period of a reference clock, comparing a vernier clock signal edge to one of the plurality of phase-delayed clock signal edges after the phase-delayed clock signal edges have been autocalibrated, and adjusting the vernier clock signal edge to match the one phase-delayed clock signal edge so that the clock edge is calibrated and available for calibrated use by a user.
Claims
exact text as granted — not AI-modified1 . A method of calibrating a timing vernier, comprising:
autocalibrating a plurality phase-delayed clock signal edges to match respective ideal signal edges, said phase-delayed clock signal edges dividing one period of a reference clock; comparing a vernier clock signal edge to one of said plurality of phase-delayed clock signal edges after said phase-delayed clock signal edges have been autocalibrated; adjusting said vernier clock signal edge to match said one phase-delayed clock signal edge; wherein said clock edge is calibrated and available for calibrated use by a user.
2 . The method of claim 1 , wherein said autocalibrating comprises:
calculating an average measurement delay between said phase-delayed clock signal edges to determine said ideal signal edges; and adjusting said plurality of phase-delayed clock edges to match said ideal signal edges.Join the waitlist — get patent alerts
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