Inventor · disambiguated record
Rajesh Tiwari
Also filed as: TIWARI RAJESH · TIWARI RAJESH K · TIWARI RAJESH KUMAR
18 granted patents·18 pending applications·293 citations·filing 1999–2022
94Inventor score
Top patents by PatentIndex Score
36 records- 0194US10471567B2CMP pad conditioning assemblyENTEGRIS INC·Filed 2016·Granted Nov 12, 2019·8 cites·13 claims
- 0292US6444569B2Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 2001·Granted Sep 3, 2002·60 cites·29 claims
- 0390US8205125B2Enhanced control in scan tests of integrated circuits with partitioned scan chainsHALES ALAN DAVID·Filed 2009·Granted Jun 19, 2012·40 cites·4 claims
- 0486US7519905B2Automatic formatting and validating of text for a markup language graphical user interfaceWEBMD CORP·Filed 2003·Granted Apr 14, 2009·70 cites·18 claims
- 0585US11333707B2Testing of integrated circuits during at-speed mode of operationTEXAS INSTRUMENTS INC·Filed 2019·Granted May 17, 2022·3 cites·18 claims
- 0685US6274478B1Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 1999·Granted Aug 14, 2001·70 cites·9 claims
- 0779US6573173B2Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 2002·Granted Jun 3, 2003·23 cites·3 claims
- 0871US11635974B2Providing a different configuration of added functionality for each of the stages of predeployment, deployment, and post deployment using a layer of abstractionORACLE INT CORP·Filed 2022·Granted Apr 25, 2023·0 cites·20 claims
- 0969US10521243B2Pre/post deployment customizationORACLE INT CORP·Filed 2017·Granted Dec 31, 2019·1 cites·18 claims
- 1068US8856601B2Scan compression architecture with bypassable scan chains for low test mode powerRAVI SRIVATHS·Filed 2010·Granted Oct 7, 2014·3 cites·7 claims
- 1167US8618661B2Die having coefficient of thermal expansion graded layerKIRKPATRICK BRIAN K·Filed 2011·Granted Dec 31, 2013·2 cites·23 claims
- 1262US11449348B2Pre/post deployment customizationORACLE INT CORP·Filed 2019·Granted Sep 20, 2022·0 cites·20 claims
- 1354US7010381B2Versatile system for controlling semiconductor topographyTEXAS INSTRUMENTS INC·Filed 2003·Granted Mar 7, 2006·4 cites·24 claims
- 1451US6941242B2Versatile system for variance-based data analysisTEXAS INSTRUMENTS INC·Filed 2003·Granted Sep 6, 2005·2 cites·35 claims
- 1551US2014154880A1Post-Polymer Revealing of Through-Substrate Via TipsTEXAS INSTRUMENTS INC·Filed 2014·Application pending·0 cites
- 1650US9972402B2Continuous write and read operations for memories with latenciesQUALCOMM INC·Filed 2016·Granted May 15, 2018·1 cites·13 claims
- 1750US2014080301A1Fabricating a semiconductor die having coefficient of thermal expansion graded layerTEXAS INSTRUMENTS INC·Filed 2013·Application pending·0 cites
- 1850US2019351527A1Conditioner for chemical-mechanical-planarization pad and related methodsENTEGRIS INC·Filed 2019·Application pending·0 cites
- 1950US2015212152A1Testing of integrated circuits during at-speed mode of operationTEXAS INSTRUMENTS INC·Filed 2015·Application pending·0 cites
- 2049US6709974B2Method of preventing seam defects in isolated linesTEXAS INSTRUMENTS INC·Filed 2002·Granted Mar 23, 2004·4 cites·14 claims
- 2146US2013062736A1Post-polymer revealing of through-substrate via tipsBRIGHTON JEFFREY E·Filed 2011·Application pending·0 cites
- 2244US2009121358A1Dual depth trench termination method for improving cu-based interconnect integrityTEXAS INSTRUMENTS INC·Filed 2008·Application pending·0 cites
- 2342US2009158156A1Online programming of operator interface panelVAIDYA VAIBHAV·Filed 2003·Application pending·0 cites
- 2441US7387960B2Dual depth trench termination method for improving Cu-based interconnect integrityTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 17, 2008·2 cites·4 claims
- 2541US2014151895A1Die having through-substrate vias with deformation protected tipsTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
- 2641US2014124900A1Through-silicon via (tsv) die and method to control warpageTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
- 2740US2013113103A1DEVICE HAVING TSVs WITH GETTERING LAYER LATERAL TO TSV TIPSWEST JEFFREY A·Filed 2012·Application pending·0 cites
- 2838US2004034833A1Dynamic interaction manager for markup language graphical user interfaceFiled 2003·Application pending·0 cites
- 2938US2004150626A1Operator interface panel with control for visibility of desplayed objectsFiled 2003·Application pending·0 cites
- 3037US2003174169A1Porting screens designed for a higher resolution HMI to a lower resolution HMIFiled 2003·Application pending·0 cites
- 3134US2010083177A1Using tags with operator interface panelsTIWARI RAJESH K·Filed 2003·Application pending·0 cites
- 3233US2018019733A1Multi-level clock gate controls to address scan mode power droop and voltage bump requirementQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3333US2016061892A1Scan programmable register controlled clock architecture for testing asynchronous domainsQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3432US2017184665A1Dynamically configurable shared scan clock channel architectureQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3528US9971663B2Method and apparatus for multiple memory shared collar architectureQUALCOMM INC·Filed 2015·Granted May 15, 2018·0 cites·6 claims
- 3624US2017110204A1Enhanced memory built-in self-test architecture for de-featured memoriesQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →