Inventor · disambiguated record
Wojciech P. Maly
Also filed as: MALY WOJCIECH · MALY WOJCIECH P
12 granted patents·1 pending application·360 citations·filing 1987–2012
93Inventor score
Files withUNIV CARNEGIE MELLON7MALY WOJCIECH P3FAIRCHILD SEMICONDUCTOR1NAT SEMICONDUCTOR CORP1PDF SOLUTIONS INC1
Top patents by PatentIndex Score
13 records- 0194US5025344ABuilt-in current testing of integrated circuitsUNIV CARNEGIE MELLON·Filed 1990·Granted Jun 18, 1991·121 cites·17 claims
- 0291US4835466AApparatus and method for detecting spot defects in integrated circuitsFAIRCHILD SEMICONDUCTOR·Filed 1987·Granted May 30, 1989·63 cites·12 claims
- 0389US5051690AApparatus and method for detecting vertically propagated defects in integrated circuitsNAT SEMICONDUCTOR CORP·Filed 1989·Granted Sep 24, 1991·53 cites·22 claims
- 0481US7770080B2Using neighborhood functions to extract logical models of physical failures using layout based diagnosisUNIV CARNEGIE MELLON·Filed 2007·Granted Aug 3, 2010·11 cites·23 claims
- 0580US9153689B2Integrated circuit device, system, and method of fabricationMALY WOJCIECH P·Filed 2011·Granted Oct 6, 2015·5 cites·14 claims
- 0680US8259286B2Lithography and associated methods, devices, and systemsMALY WOJCIECH P·Filed 2005·Granted Sep 4, 2012·6 cites·20 claims
- 0773US5051951AStatic RAM memory cell using N-channel MOS transistorsUNIV CARNEGIE MELLON·Filed 1991·Granted Sep 24, 1991·42 cites·6 claims
- 0865US9640653B2Integrated circuit device, system, and method of fabricationMALY WOJCIECH P·Filed 2012·Granted May 2, 2017·1 cites·19 claims
- 0961US6892367B2Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layoutPDF SOLUTIONS INC·Filed 2002·Granted May 10, 2005·13 cites·15 claims
- 1061US6175244B1Current signatures for IDDQ testingUNIV CARNEGIE MELLON·Filed 1997·Granted Jan 16, 2001·23 cites·13 claims
- 1157US5324992ASelf-timing integrated circuits having low clock signal during inactive periodsUNIV CARNEGIE MELLON·Filed 1992·Granted Jun 28, 1994·13 cites·11 claims
- 1248US2009321830A1Integrated circuit device, system, and method of fabricationUNIV CARNEGIE MELLON·Filed 2007·Application pending·0 cites
- 1337US5528604ATest pattern generation for an electronic circuit using a transformed circuit descriptionUNIV CARNEGIE MELLON·Filed 1995·Granted Jun 18, 1996·9 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →