Integrated circuit device, system, and method of fabrication

Abstract

A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portions that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.

1 . A semiconductor device, comprising:
 a first semiconductor portion having a first end, a second end, and a slit portion between the first end and the second end, wherein the first end has a width, wherein the second end has a width, wherein the slit portion has a width, wherein the width of the slit portion is less than the width of at least one of the first end and the second end, and wherein the width of the first end, the second end, and the slit portions are measured in a direction transverse to an imaginary line between the first end and the second end;   a second portion, wherein the second portion is a different material than that of the first semiconductor portion;   a third portions, wherein the second and third portions are on opposite sides of the slit portion, and wherein the third portion is a different material than that of the first semiconductor portion;   at least three terminals selected from a group consisting of:
 a first terminal connected to the first end; 
   a second terminal connected to the second end;   a third terminal connected to the second portion; and   a fourth terminal connected to the third portion.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the slit portion is doped differently than the first end. 
   
   
       3 . The semiconductor device of  claim 2 , wherein one of the first end and the slit portion includes a p-type dopant, and the other of the first end and the slit portion includes an n-type dopant. 
   
   
       4 . The semiconductor device of  claim 2 , wherein the first ends has a different dopant concentration than the slit portion. 
   
   
       5 . The semiconductor device of  claim 1 , wherein:
 the first semiconductor portion is single crystal silicon;   the second portion is selected from a group comprising polysilicon and metal; and   the third portion is selected from a group comprising polysilicon and metal.   
   
   
       6 . The semiconductor device of  claim 1 , wherein:
 the first semiconductor portion is doped silicon;   the second portion is doped silicon; and   the third portion is doped silicon, wherein the dopant in the first semiconductor portion different than the dopant in the second and third portions.   
   
   
       7 . The semiconductor device of  claim 1 , wherein the device includes the first, second, and third terminals, and further comprising an electrical insulators between the third terminal and the first semiconductor portion. 
   
   
       8 . The semiconductor device of  claim 7 , wherein the third portion is completely surrounded by an electrical insulator. 
   
   
       9 . The semiconductor device of  claim 7 , wherein the third portion is not electrically connected to a terminal. 
   
   
       10 . The semiconductor device of  claim 7 , further comprising:
 the fourth terminal; and   an electrical insulator between the fourth terminal and the first semiconductor portion.   
   
   
       11 . The semiconductor device of  claim 1 , wherein:
 the device includes the first, third, and fourth terminals; and   the third and fourth terminals are electrically connected to the first semiconductor portion.   
   
   
       12 . The semiconductor device of  claim 11 , wherein:
 the third terminal and the first semiconductor portion are electrically connected through a semiconductor p-n junction; and   the fourth terminal and the first semiconductor portion are electrically connected through a semiconductor p-n junction.   
   
   
       13 . The semiconductor device of  claim 1 , wherein:
 the device includes the first, second, third, and fourth terminals;   the width of the slit portion is less than the width of both the first and the second end of the first semiconductor portion.   
   
   
       14 . The semiconductor device of  claim 1 , further comprising:
 at least one of the first semiconductor portion, the second portion, and the third portion has a top surface and a bottom surface;   at least one of the terminals extends from the top surface to the bottom surface.   
   
   
       15 . The semiconductor device of  claim 14 , further comprising:
 a top interconnect connected to the at least one of the terminals at the top surface; and   a bottom interconnect connected to the at least one of the terminals at the bottom surface.   
   
   
       16 . The semiconductor device of  claim 1 , wherein:
 the first semiconductor portion has a top surface;   the second portion has a top surface;   the third portion has a top surface;   the top surfaces of the first semiconductor portion, the second portion, and the third portion are all parallel to each other   
   
   
       17 . The semiconductor device of  claim 16 , wherein the top surfaces of the first semiconductor portion, the second portion, and the third portion lie in a common imaginary plane. 
   
   
       18 . The semiconductor device of  claim 17 , wherein:
 the first end of the first semiconductor portion has a top surface;   the second end of the first semiconductor portion has a top surface;   the slit portion of the first semiconductor portion has a top surface; and   the top surfaces of the first end, second end, and slit portion lie in the common imaginary plane   
   
   
       19 . The semiconductor device of  claim 16 , wherein the at least three of the terminals contact the common imaginary plane. 
   
   
       20 . The semiconductor device of  claim 1 , wherein the second and third portions are metal. 
   
   
       21 - 36 . (canceled)