Inventor · disambiguated record
Chang-Jen Hsieh
Also filed as: HSIEH CHANG-JEN
7 granted patents·3 pending applications·36 citations·filing 2004–2025
82Inventor score
Top patents by PatentIndex Score
10 records- 0192US11785862B2Via landing enhancement for memory deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Oct 10, 2023·2 cites·20 claims
- 0288US8809179B2Method for reducing topography of non-volatile memory and resulting memory cellsWANG SHIH WEI·Filed 2007·Granted Aug 19, 2014·15 cites·20 claims
- 0386US7667261B2Split-gate memory cells and fabrication methods thereofTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 23, 2010·9 cites·18 claims
- 0483US11031543B2Via landing enhancement for memory deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 8, 2021·3 cites·20 claims
- 0574US2025324915A1Manufacturing method of memory device with removal of top electrodeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0671US7652318B2Split-gate memory cells and fabrication methods thereofTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Jan 26, 2010·3 cites·15 claims
- 0764US2022352457A1Memory device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Application pending·0 cites
- 0860US7951670B2Flash memory cell with split gate structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted May 31, 2011·2 cites·8 claims
- 0951US2007181936A1Novel architecture to monitor isolation integrity between floating gate and source lineTAIWAN SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 1049US7226828B2Architecture to monitor isolation integrity between floating gate and source lineTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jun 5, 2007·2 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →