Inventor · disambiguated record
Sameer H. Jain
Also filed as: JAIN SAMEER · JAIN SAMEER H · JAIN SAMEER HEMCHAND
22 granted patents·3 pending applications·129 citations·filing 2006–2019
94Inventor score
Top patents by PatentIndex Score
25 records- 0195US9111962B1Selective dielectric spacer deposition for exposing sidewalls of a finFETIBM·Filed 2014·Granted Aug 18, 2015·18 cites·17 claims
- 0295US8421077B2Replacement gate MOSFET with self-aligned diffusion contactJAIN SAMEER H·Filed 2010·Granted Apr 16, 2013·35 cites·20 claims
- 0393US8951868B1Formation of functional gate structures with different critical dimensions using a replacement gate processIBM·Filed 2013·Granted Feb 10, 2015·19 cites·19 claims
- 0490US9349836B2Fin end spacer for preventing merger of raised active regionsIBM·Filed 2014·Granted May 24, 2016·6 cites·11 claims
- 0588US9875939B1Methods of forming uniform and pitch independent fin recessGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 23, 2018·5 cites·20 claims
- 0688US8629510B2Two-step silicide formationIBM·Filed 2013·Granted Jan 14, 2014·7 cites·6 claims
- 0782US8236637B2Planar silicide semiconductor structureUTOMO HENRY K·Filed 2010·Granted Aug 7, 2012·7 cites·8 claims
- 0881US8647954B2Two-step silicide formationIBM·Filed 2013·Granted Feb 11, 2014·4 cites·6 claims
- 0981US7538339B2Scalable strained FET device and method of fabricating the sameIBM·Filed 2006·Granted May 26, 2009·7 cites·5 claims
- 1079US8652914B2Two-step silicide formationALPTEKIN EMRE·Filed 2011·Granted Feb 18, 2014·4 cites·12 claims
- 1175US9331166B2Selective dielectric spacer deposition for exposing sidewalls of a finFETIBM·Filed 2014·Granted May 3, 2016·2 cites·19 claims
- 1274US8642424B2Replacement metal gate structure and methods of manufactureJAIN SAMEER H·Filed 2011·Granted Feb 4, 2014·4 cites·22 claims
- 1374US7615435B2Semiconductor device and method of manufactureIBM·Filed 2007·Granted Nov 10, 2009·4 cites·1 claims
- 1472US10262996B2Third type of metal gate stack for CMOS devicesIBM·Filed 2017·Granted Apr 16, 2019·1 cites·14 claims
- 1561US10741554B2Third type of metal gate stack for CMOS devicesIBM·Filed 2019·Granted Aug 11, 2020·0 cites·19 claims
- 1660US7687338B2Method of reducing embedded SiGe loss in semiconductor device manufacturingIBM·Filed 2007·Granted Mar 30, 2010·6 cites·20 claims
- 1759US9679993B2Fin end spacer for preventing merger of raised active regionsIBM·Filed 2016·Granted Jun 13, 2017·0 cites·16 claims
- 1858US9601380B2Fin end spacer for preventing merger of raised active regionsIBM·Filed 2015·Granted Mar 21, 2017·0 cites·16 claims
- 1958US9515168B2Fin end spacer for preventing merger of raised active regionsIBM·Filed 2015·Granted Dec 6, 2016·0 cites·15 claims
- 2058US9391175B2Fin end spacer for preventing merger of raised active regionsIBM·Filed 2015·Granted Jul 12, 2016·0 cites·17 claims
- 2155US9634006B2Third type of metal gate stack for CMOS devicesIBM·Filed 2014·Granted Apr 25, 2017·0 cites·13 claims
- 2246US2009146223A1Process and method to lower contact resistanceIBM·Filed 2007·Application pending·0 cites
- 2346US2009166770A1Method of fabricating gate electrode for gate of mosfet and structure thereofIBM·Filed 2008·Application pending·0 cites
- 2443US2007212861A1Laser surface annealing of antimony doped amorphized semiconductor regionIBM·Filed 2006·Application pending·0 cites
- 2538US9514992B2Unidirectional spacer in trench silicideIBM·Filed 2015·Granted Dec 6, 2016·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →