Inventor · disambiguated record
Yervant Zorian
Also filed as: ZORIAN YERVANT
48 granted patents·1 pending application·918 citations·filing 1990–2023
98Inventor score
Files withSYNOPSYS INC17VIRAGE LOGIC CORP12LUCENT TECHNOLOGIES INC6AGERE SYST GUARDIAN CORP3AMIRKHANYAN KAREN2
Top patents by PatentIndex Score
49 records- 0196US7590902B1Methods and apparatuses for external delay test of input-output circuitsVIRAGE LOGIC CORP·Filed 2006·Granted Sep 15, 2009·25 cites·21 claims
- 0293US7415640B1Methods and apparatuses that reduce the size of a repair data container for repairable memoriesVIRAGE LOGIC CORP·Filed 2003·Granted Aug 19, 2008·86 cites·35 claims
- 0391US5107501ABuilt-in self-test technique for content-addressable memoriesAT & T BELL LAB·Filed 1990·Granted Apr 21, 1992·90 cites·11 claims
- 0489US8225156B1Methods and apparatuses for external voltage test methodology of input-output circuitsTABATABAEI SASSAN·Filed 2010·Granted Jul 17, 2012·5 cites·20 claims
- 0589US7127647B1Apparatus, method, and system to allocate redundant componentsVIRAGE LOGIC CORP·Filed 2001·Granted Oct 24, 2006·45 cites·35 claims
- 0688US7237154B1Apparatus and method to generate a repair signatureVIRAGE LOGIC CORP·Filed 2002·Granted Jun 26, 2007·47 cites·24 claims
- 0786US7290186B1Method and apparatus for a command based bist for testing memoriesVIRAGE LOGIC CORP·Filed 2003·Granted Oct 30, 2007·45 cites·25 claims
- 0886US7149924B1Apparatus, method, and system having a pin to activate the self-test and repair instructionsVIRAGE LOGIC CORP·Filed 2002·Granted Dec 12, 2006·42 cites·19 claims
- 0985US12094548B1Diagnosing faults in memory periphery circuitrySYNOPSYS INC·Filed 2023·Granted Sep 17, 2024·1 cites·20 claims
- 1085US7673264B1System and method for verifying IP integrity in system-on-chip (SOC) designVIRAGE LOGIC CORP·Filed 2007·Granted Mar 2, 2010·22 cites·22 claims
- 1185US6205564B1Optimized built-in self-test method and apparatus for random access memoriesLUCENT TECHNOLOGIES INC·Filed 1997·Granted Mar 20, 2001·65 cites·37 claims
- 1283US9541591B2Periodic signal measurement using statistical samplingSYNOPSYS INC·Filed 2015·Granted Jan 10, 2017·3 cites·19 claims
- 1381US7519888B2Input-output device testingVIRAGE LOGIC CORP·Filed 2006·Granted Apr 14, 2009·10 cites·21 claims
- 1481US7149921B1Apparatus, method, and system to allocate redundant components with subsets of the redundant componentsVIRAGE LOGIC CORP·Filed 2002·Granted Dec 12, 2006·26 cites·25 claims
- 1580US9336342B2Memory hard macro partition optimization for testing embedded memoriesZORIAN YERVANT·Filed 2011·Granted May 10, 2016·9 cites·9 claims
- 1679US11023310B1Detection of address errors in memory devices using multi-segment error detection codesSYNOPSYS INC·Filed 2019·Granted Jun 1, 2021·3 cites·20 claims
- 1778US7768840B1Memory modeling using an intermediate level structural descriptionVIRAGE LOGIC CORP·Filed 2007·Granted Aug 3, 2010·13 cites·19 claims
- 1878US7415641B1System and method for repairing a memoryVIRAGE LOGIC CORP·Filed 2003·Granted Aug 19, 2008·23 cites·14 claims
- 1977US7856581B1Methods and apparatuses for external test methodology and initialization of input-output circuitsSYNOPSYS INC·Filed 2006·Granted Dec 21, 2010·4 cites·29 claims
- 2076US7898882B2Architecture, system and method for compressing repair data in an integrated circuit (IC) designSYNOPSYS INC·Filed 2007·Granted Mar 1, 2011·9 cites·15 claims
- 2176US6397349B2Built-in self-test and self-repair methods and devices for computer memories comprising a reconfiguration memory deviceAGERE SYST GUARDIAN CORP·Filed 1998·Granted May 28, 2002·39 cites·16 claims
- 2276US5513318AMethod for built-in self-testing of ring-address FIFOsAT & T CORP·Filed 1994·Granted Apr 30, 1996·47 cites·12 claims
- 2375US11527298B1On-chip memory diagnosticsSYNOPSYS INC·Filed 2021·Granted Dec 13, 2022·1 cites·20 claims
- 2475US8112730B2Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilersALEKSANYAN KAREN·Filed 2008·Granted Feb 7, 2012·12 cites·17 claims
- 2574US6330696B1Self-testing of DRAMs for multiple faultsAGERE SYST GUARDIAN CORP·Filed 1998·Granted Dec 11, 2001·37 cites·5 claims
- 2673US10115477B2FinFET-based memory testing using multiple read operationsSYNOPSYS INC·Filed 2017·Granted Oct 30, 2018·3 cites·8 claims
- 2773US7890900B2Various methods and apparatuses for effective yield enhancement of good chip dies having memories per waferSYNOPSYS INC·Filed 2008·Granted Feb 15, 2011·8 cites·18 claims
- 2869US5091908ABuilt-in self-test technique for read-only memoriesAT & T BELL LAB·Filed 1990·Granted Feb 25, 1992·29 cites·7 claims
- 2967US8295108B2Architecture, system and method for compressing repair data in an integrated circuit (IC) designDARBINYAN KAREN·Filed 2011·Granted Oct 23, 2012·4 cites·17 claims
- 3067US5978935AMethod for built-in self-testing of ring-address FIFOs having a data input register with transparent latchesLUCENT TECHNOLOGIES INC·Filed 1997·Granted Nov 2, 1999·27 cites·20 claims
- 3166US6317846B1System and method for detecting faults in computer memories using a look up tableAGERE SYST GUARDIAN CORP·Filed 1998·Granted Nov 13, 2001·24 cites·13 claims
- 3265US8359553B1Various methods and apparatuses for effective yield enhancement of good chip dies having memories per waferSYNOPSYS INC·Filed 2011·Granted Jan 22, 2013·3 cites·15 claims
- 3364US8850277B2Detecting random telegraph noise induced failures in an electronic memoryAMIRKHANYAN KAREN·Filed 2011·Granted Sep 30, 2014·4 cites·33 claims
- 3462US5381419AMethod and apparatus for detecting retention faults in memoriesAT & T CORP·Filed 1993·Granted Jan 10, 1995·22 cites·11 claims
- 3561US5978947ABuilt-in self-test in a plurality of stages controlled by a token passing network and methodLUCENT TECHNOLOGIES INC·Filed 1997·Granted Nov 2, 1999·23 cites·28 claims
- 3660US9514258B2Generation of memory structural model based on memory layoutAMIRKHANYAN KAREN·Filed 2012·Granted Dec 6, 2016·2 cites·21 claims
- 3760US7853847B1Methods and apparatuses for external voltage test of input-output circuitsSYNOPSYS INC·Filed 2006·Granted Dec 14, 2010·1 cites·20 claims
- 3858US12002530B2Embedded memory transparent in-system built-in self-testSYNOPSYS INC·Filed 2022·Granted Jun 4, 2024·0 cites·20 claims
- 3958US7788551B2System and method for repairing a memoryVIRAGE LOGIC CORP·Filed 2008·Granted Aug 31, 2010·3 cites·7 claims
- 4056US12469527B2In situ delay measurements on integrated circuits using live data and pulse width modulationSYNOPSYS INC·Filed 2023·Granted Nov 11, 2025·0 cites·18 claims
- 4150US5570374ABuilt-in self-test control networkLUCENT TECHNOLOGIES INC·Filed 1993·Granted Oct 29, 1996·23 cites·5 claims
- 4247US12266413B2Built-in self-test circuit for row hammering in memorySYNOPSYS INC·Filed 2022·Granted Apr 1, 2025·0 cites·16 claims
- 4344US10192635B1FinFET-based memory testing using multiple read operationsSYNOPSYS INC·Filed 2018·Granted Jan 29, 2019·0 cites·20 claims
- 4444US9831000B2Testing electronic memories based on fault and test algorithm periodicitySYNOPSYS INC·Filed 2014·Granted Nov 28, 2017·0 cites·21 claims
- 4543US6237123B1Built-in self-test controlled by a token network and methodLUCENT TECHNOLOGIES INC·Filed 1997·Granted May 22, 2001·17 cites·9 claims
- 4638US2013019130A1Testing electronic memories based on fault and test algorithm periodicitySYNOPSYS INC·Filed 2011·Application pending·0 cites
- 4735US10789398B2Method and apparatus for SOC with optimal RSMASYNOPSYS INC·Filed 2017·Granted Sep 29, 2020·0 cites·4 claims
- 4835US5960009ABuilt in shelf test method and apparatus for booth multipliersLUCENT TECHNOLOGIES INC·Filed 1996·Granted Sep 28, 1999·16 cites·39 claims
- 4934US9053050B2Determining a desirable number of segments for a multi-segment single error correcting coding schemeGRIGORYAN HAYK·Filed 2011·Granted Jun 9, 2015·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →