Testing electronic memories based on fault and test algorithm periodicity

Abstract

Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.

1 . A processor unit for testing an electronic memory, the processor unit comprising:
 a built-in self-test (BIST) finite state machine that coordinates a plurality of BIST functions of the processor unit;   an address generator in communication with the BIST finite state machine to generate addresses of memory cells for the testing;   a data generator in communication with the BIST finite state machine that generates data patterns to be applied to the electronic memory;   a test algorithm generation unit that generates March tests to be applied to the electronic memory;   a programmable test algorithm register in communication with the test algorithm generation unit that stores one or more March elements generated by the test algorithm generator unit; and   a test algorithm register control unit, coupled between the BIST finite state machine and the programmable test algorithm register, that enables the BIST finite state machine to determine presence of the one or more March elements stored in the programmable test algorithm register.   
     
     
         2 . The processor unit as claimed in claim Error! Reference source not found., wherein the processor unit comprises an application specific integrated circuit. 
     
     
         3 . The processor unit as claimed in  claim 1 , wherein the test algorithm generation unit comprises a fault periodic table unit and a test algorithm template unit. 
     
     
         4 . The processor unit as claimed in  claim 3 , wherein the fault periodic table unit comprises a plurality of columns, each of the plurality of columns corresponding to a functionality of a test mechanism, and a plurality of rows, each of the plurality of rows corresponding to a fault family. 
     
     
         5 . The processor unit as claimed in  claim 3 , wherein the test algorithm template unit comprises a sequence of test operations, an initial value of a faulty memory cell, a final value of a faulty memory cell upon completion of the sequence of test operations, and a March test. 
     
     
         6 . The processor unit as claimed in  claim 1 , wherein the data generator comprises a programmable background pattern register, a predefined background pattern register, and a multiplexer responsive to a pattern type command from the BIST finite state machine to select the test data output from one of the programmable background pattern register and the predefined background pattern register. 
     
     
         7 . The processor unit as claimed in  claim 1 , wherein the programmable test algorithm register comprises at least one March element descriptor and a plurality of March operation descriptors. 
     
     
         8 . The processor unit as claimed in claim Error! Reference source not found., wherein the March element descriptor comprises a plurality of sub-fields indicating marker, pattern type, addressing mode, addressing type, addressing direction, and number of operations. 
     
     
         9 . The processor unit as claimed in  claim 7 , wherein the plurality of March operation descriptors comprises an inverse pattern sub-field and opcode sub-fields. 
     
     
         10 . The processor unit as claimed in  claim 7 , wherein the plurality of March operation descriptors comprises one or more of a memory-enable operation code, a memory-read operation code, and a memory-write operation code. 
     
     
         11 . The processor unit as claimed in  claim 1 , wherein the test algorithm register control unit enables configuration of the address generator and the data generator prior to test operation execution, and provides to the BIST finite state machine control over the programmable test algorithm register. 
     
     
         12 . The processor unit as claimed in  claim 1 , wherein the BIST finite state machine extends over a sequence of states that comprises
 an idle state wherein the BIST finite state machine awaits an external signal to start performing the plurality of BIST functions,   a reset state wherein the BIST finite state machine resets a plurality of registers within the processor unit, and into which state the BIST finite state machine enters upon exiting the idle state,   a check state wherein the BIST finite state machine checks the one or more March elements stored in the programmable test algorithm register, and into which state the BIST finite state machine enters upon exiting the reset state,   an exec state wherein the BIST finite state machine executes the one or more March elements checked in the check state, and into which state the BIST finite state machine enters upon exiting the check state,   a shift state wherein the BIST finite state machine shifts the programmable test algorithm register to a next sequential element, and into which state the BIST finite state machine enters upon exiting the exec state if the next sequential element is included in the programmable test algorithm register,   a roll state wherein the BIST finite state machine shifts the programmable test algorithm register to a starting position, and into which state the BIST finite state machine enters upon exiting the exec state if the next sequential element is excluded in the programmable test algorithm register,   a done state wherein the BIST finite state machine awaits the de-assertion of the external signal indicating start of the plurality of BIST functions, into which state the BIST finite state machine enters upon exiting the roll state, and from which state the BIST finite state machine enters the idle state upon the de-assertion of the external signal.   
     
     
         13 . A memory wrapper unit for testing an electronic memory, the memory wrapper unit comprising:
 an operation decoder that interprets an operation code;   a data comparator that compares a test data output with a data output from the electronic memory under test; and   the electronic memory under test being in communication with the operation decoder and the data comparator.   
     
     
         14 . The memory wrapper unit as claimed in  claim 13 , wherein the operation decoder comprises a programmable operations register, a predefined operations register, and a multiplexer responsive to an operation code command to select a memory control signal to be transmitted to the electronic memory from one of the programmable operations register and the predefined operations register. 
     
     
         15 . The memory wrapper unit as claimed in  claim 14 , wherein the programmable operations register comprises a table that maps programmable codes to operations on the electronic memory under test. 
     
     
         16 . The memory wrapper unit as claimed in  claim 13 , wherein the operation code is received from a built-in self-test (BIST) finite state machine in a processor unit. 
     
     
         17 . The memory wrapper unit as claimed in  claim 13 , wherein the test data output is received from a data generator in a processor unit. 
     
     
         18 . The memory wrapper unit as claimed in  claim 13 , wherein the electronic memory under test is in communication with an address generator and a data generator comprised in a processor unit. 
     
     
         19 . A method of testing an electronic memory, the method comprising:
 constructing a fault periodic table having a plurality of columns and a plurality of rows, each of the plurality of columns corresponding with a functionality of a test mechanism of a plurality of test mechanisms, and each of the plurality of rows corresponding with a fault family of a plurality of fault families;   selecting a first March test sequence according to a first fault family of the plurality of fault families and a first test mechanism of the plurality of test mechanisms;   applying the first March test sequence to the electronic memory;   selecting a second March test sequence according to a second fault family of the plurality of fault families and a second test mechanism of the plurality of test mechanisms;   applying the second March test sequence to the electronic memory; and   determining if the electronic memory under test is one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.   
     
     
         20 . The method as claimed in  claim 19 , wherein the test mechanism comprises one or more of a background pattern, an addressing mode, an addressing type, and concurrency of operations within the test mechanism. 
     
     
         21 . The method as claimed in  claim 19 , wherein the electronic memory is tested for the plurality of fault families. 
     
     
         22 . The method as claimed in  claim 21 , wherein the electronic memory is unacceptable based on failure of one or more of the first March test sequence and the second March test sequence. 
     
     
         23 . The method as claimed in  claim 19 , wherein the results are used to extend the fault periodic table by creating a new fault family. 
     
     
         24 . The method as claimed in  claim 19 , wherein the results are used to extend the fault periodic table by creating another test mechanism. 
     
     
         25 . The method as claimed in  claim 19 , wherein the first March test sequence and the second March test sequence each represent a March test. 
     
     
         26 . The method as claimed in  claim 25 , wherein the March test is generated by:
 writing a final value of a faulty memory cell along an arbitrary order of addresses,   executing a sequence of test operations along the increasing order of the addresses,   executing a logical opposite of the sequence of test operations along the increasing order of the addresses,   executing the sequence of test operations along a decreasing order of the addresses,   executing the logical opposite of the sequence of test operations along the decreasing order of the addresses, and   reading the final value of the faulty memory cell along the arbitrary order of the addresses.   
     
     
         27 . The method as claimed in  claim 26 , wherein the March test is executed if an initial value of the faulty memory cell equals the final value of the faulty memory cell and if a first operation of the sequence of test operations is a read operation. 
     
     
         28 . The method as claimed in  claim 26 , wherein the March test is one of
   (W(A1));  (TO);  (˜TO);  (TO);  (˜TO);  (R(A1)),     (W(A1));  (TO);  (˜TO);  (TO);  (˜TO);  (R(A1)),     (W(A1));  (TO);  (˜TO);  (TO);  (˜TO);  (R(A1)), and     (W(A1));  (TO);  (˜TO);  (TO);  (˜TO);  (R(A1)).   
     
     
         29 . The method as claimed in  claim 25 , wherein the March test is generated by:
 writing a final value of a faulty memory cell along an arbitrary order of addresses,   reading the final value of the faulty memory cell to execute a sequence of test operations along the increasing order of the addresses,   reading a logical opposite of the final value of the faulty memory cell to execute a logical opposite of the sequence of test operations along the increasing order of the addresses,   reading the final value of the faulty memory cell to execute the sequence of test operations along a decreasing order of the addresses,   reading the logical opposite of the final value of the faulty memory cell to execute the logical opposite of the sequence of test operations along the decreasing order of the addresses, and   reading the final value of the faulty memory cell along the arbitrary order of the addresses.   
     
     
         30 . The method as claimed in  claim 28 , wherein the March test is executed if an initial value of the faulty memory cell equals the final value of the faulty memory cell and if a first operation of the sequence of test operations is other than a read operation. 
     
     
         31 . The method as claimed in  claim 29 , wherein the March test is one of
   (W(A1));  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1)), and     (W(A1));  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1)), and     (W(A1));  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1)), and     (W(A1));  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1), TO);  (R(˜A1), ˜TO);  (R(A1)).   
     
     
         32 . The method as claimed in  claim 25 , wherein the March test is generated by:
 writing a final value of a faulty memory cell along an arbitrary order of addresses,   reading the final value of the faulty memory cell to subsequently write an initial value of the faulty memory cell and execute a sequence of test operations along the increasing order of the addresses,   reading a logical opposite of the final value of the faulty memory cell to subsequently write a logical opposite of the initial value of the faulty memory cell and execute a logical opposite of the sequence of test operations along the increasing order of the addresses,   reading the final value of the faulty memory cell to subsequently write the initial value of the faulty memory cell and execute the sequence of test operations along a decreasing order of the addresses,   reading the logical opposite of the final value of the faulty memory cell to subsequently write the logical opposite of the initial value of the faulty memory cell and execute the logical opposite of the sequence of test operations along the decreasing order of the addresses, and   reading the final value of the faulty memory cell along the arbitrary order of the addresses.   
     
     
         33 . The method as claimed in  claim 30 , wherein the March test is executed if the initial value of the faulty memory cell is unequal to the final value of the faulty memory cell. 
     
     
         34 . The method as claimed in  claim 32 , wherein the March test is one of
   (W(A1));  (R(A1), W(A2), TO);  (R(˜A1), W(˜A2), ˜TO);  (R(A1), W(A2), TO));  (R(˜A1), W(˜A2), ˜TO);  (R(A1)),     (W(A1));  (R(A1), W(A2), TO);  (R(˜A1), W(˜A2), ˜TO);  (R(A1), W(A2), TO));  (R(˜A1), W(˜A2), ˜TO);  (R(A1)),     (W(A1));  (R(A1), W(A2), TO);  (R(˜A1), W(˜A2), ˜TO);  (R(A1), W(A2), TO));  (R(˜A1), W(˜A2), ˜TO);  (R(A1)),     (W(A1));  (R(A1), W(A2), TO);  (R(˜A1), W(˜A2), ˜TO);  (R(A1), W(A2), TO));  (R(˜A1), W(˜A2), ˜TO);  (R(A1)).