Inventor · disambiguated record
John M. Danskin
Also filed as: DANSKIN JOHN · DANSKIN JOHN M
31 granted patents·2 pending applications·791 citations·filing 2001–2015
97Inventor score
Top patents by PatentIndex Score
33 records- 0198US6646639B1Modified method and apparatus for improved occlusion culling in graphics systemsNVIDIA CORP·Filed 2001·Granted Nov 11, 2003·196 cites·17 claims
- 0297US6959110B1Multi-mode texture compression algorithmNVIDIA CORP·Filed 2001·Granted Oct 25, 2005·123 cites·26 claims
- 0397US6894689B1Occlusion culling method and apparatus for graphics systemsNVIDIA CORP·Filed 2003·Granted May 17, 2005·115 cites·94 claims
- 0495US7830392B1Connecting multiple pixel shaders to a frame buffer without a crossbarNVIDIA CORP·Filed 2006·Granted Nov 9, 2010·16 cites·10 claims
- 0593US8095782B1Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context changeDANSKIN JOHN M·Filed 2007·Granted Jan 10, 2012·38 cites·20 claims
- 0693US8040349B1System and method for structuring an A-bufferNVIDIA CORP·Filed 2007·Granted Oct 18, 2011·31 cites·20 claims
- 0793US7098922B1Multiple data buffers for processing graphics dataNVIDIA CORP·Filed 2003·Granted Aug 29, 2006·58 cites·19 claims
- 0890US8730249B2Parallel array architecture for a graphics processorDANSKIN JOHN M·Filed 2011·Granted May 20, 2014·6 cites·17 claims
- 0990US8327071B1Interprocessor direct cache writesDANSKIN JOHN M·Filed 2007·Granted Dec 4, 2012·25 cites·20 claims
- 1088US8130223B1System and method for structuring an A-buffer to support multi-sample anti-aliasingDANSKIN JOHN M·Filed 2008·Granted Mar 6, 2012·18 cites·21 claims
- 1187US8775229B1Method of correcting a project scheduleDANSKIN JOHN M·Filed 2006·Granted Jul 8, 2014·17 cites·10 claims
- 1286US8553041B1System and method for structuring an A-buffer to support multi-sample anti-aliasingDANSKIN JOHN M·Filed 2008·Granted Oct 8, 2013·16 cites·23 claims
- 1384US7586492B2Real-time display post-processing using programmable hardwareNVIDIA CORP·Filed 2004·Granted Sep 8, 2009·25 cites·26 claims
- 1483US8026912B1System and method for structuring an A-bufferNVIDIA CORP·Filed 2007·Granted Sep 27, 2011·12 cites·20 claims
- 1582US7979683B1Multiple simultaneous context architectureNVIDIA CORP·Filed 2007·Granted Jul 12, 2011·11 cites·20 claims
- 1681US8139069B1Method and system for improving data coherency in a parallel rendering systemMOLNAR STEVEN E·Filed 2006·Granted Mar 20, 2012·10 cites·12 claims
- 1780US8654135B1A-Buffer compression for different compression formatsDANSKIN JOHN M·Filed 2009·Granted Feb 18, 2014·10 cites·24 claims
- 1879US8085272B1Method and system for improving data coherency in a parallel rendering systemMOLNAR STEVEN E·Filed 2006·Granted Dec 27, 2011·10 cites·14 claims
- 1978US7554546B1Stippled lines using direct distance evaluationNVIDIA CORP·Filed 2007·Granted Jun 30, 2009·7 cites·27 claims
- 2075US8427496B1Method and system for implementing compression across a graphics bus interconnectTAMASI ANTHONY MICHAEL·Filed 2005·Granted Apr 23, 2013·8 cites·19 claims
- 2175US7342590B1Screen compressionNVIDIA CORP·Filed 2003·Granted Mar 11, 2008·12 cites·20 claims
- 2272US7221368B1Stippled lines using direct distance evaluationNVIDIA CORP·Filed 2003·Granted May 22, 2007·14 cites·28 claims
- 2371US8077174B2Hierarchical processor arrayLINDHOLM JOHN ERIK·Filed 2007·Granted Dec 13, 2011·4 cites·25 claims
- 2467US7965895B1Screen compressionNVIDIA CORP·Filed 2007·Granted Jun 21, 2011·1 cites·13 claims
- 2564US7622947B1Redundant circuit presents connections on specified I/O portsNVIDIA CORP·Filed 2006·Granted Nov 24, 2009·5 cites·11 claims
- 2658US2007159488A1Parallel Array Architecture for a Graphics ProcessorNVIDIA CORP·Filed 2006·Application pending·0 cites
- 2751US8379033B2Method and system for improving data coherency in a parallel rendering systemNVIDIA CORP·Filed 2012·Granted Feb 19, 2013·0 cites·20 claims
- 2851US8237705B2Hierarchical processor arrayLINDHOLM JOHN ERIK·Filed 2011·Granted Aug 7, 2012·0 cites·20 claims
- 2950US6980208B1System and method for enhancing depth value processing in a graphics pipelineNVIDIA CORP·Filed 2002·Granted Dec 27, 2005·3 cites·59 claims
- 3048US7907145B1Multiple data buffers for processing graphics dataNVIDIA CORP·Filed 2006·Granted Mar 15, 2011·0 cites·19 claims
- 3147US9727463B2Assymetric coherent caching for heterogeneous computingNVIDIA CORP·Filed 2015·Granted Aug 8, 2017·0 cites·20 claims
- 3245US9092170B1Method and system for implementing fragment operation processing across a graphics bus interconnectDANSKIN JOHN M·Filed 2005·Granted Jul 28, 2015·0 cites·31 claims
- 3345US2007268298A1Delayed frame buffer merging with compressionALBEN JONAH M·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →