Parallel Array Architecture for a Graphics Processor

Abstract

A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. The pixel distribution logic selects one of the processing clusters to which the coverage data for a first pixel is delivered based at least in part on a location of the first pixel within an image area. The processing clusters can be mapped directly to the frame buffers partitions without a crossbar so that pixel data is delivered directly from the processing cluster to the appropriate frame buffer partitions. Alternatively, a crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions. The crossbar is configured such that pixel data generated by any one of the processing clusters is deliverable to any one of the frame buffer partitions.

1 . A graphics processor comprising: 
 a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data;    a rasterizer configured to generate coverage data for each of a plurality of pixels; and    pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array,    wherein the pixel distribution logic selects the one of the processing clusters to which the coverage data for a first pixel is delivered based at least in part on a location of the first pixel within an image area.    
   
   
       2 . The graphics processor of  claim 1  wherein the image area is divided into a plurality of tiles, each tile being assigned to one of the processing clusters, and wherein the pixel distribution logic selects the one of the processing clusters based on a determination as to which of the plurality of tiles includes the first pixel.  
   
   
       3 . The graphics processor of  claim 2  wherein at least two of the plurality of tiles are assigned to each of the processing clusters, wherein for each processing cluster, the tiles assigned thereto are not contiguous with each other.  
   
   
       4 . The graphics processor of  claim 1  wherein each of the processing clusters is configured to deliver pixel data to a respective one of a plurality of partitions of a frame buffer.  
   
   
       5 . The graphics processor of  claim 1  further comprising a crossbar coupled to each of the processing clusters and configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.  
   
   
       6 . The graphics processor of  claim 5  wherein the crossbar is configured such that pixel data generated by any one of the processing clusters is deliverable to any one of the frame buffer partitions.  
   
   
       7 . The graphics processor of  claim 1  wherein each processing core is also operable to execute vertex shader programs and geometry shader programs.