Inventor · disambiguated record
Mohamad A. Shaheen
Also filed as: SHAHEEN MOHAMAD · SHAHEEN MOHAMAD A · SIMON LEGAL REPRESENTATIVE DAVID
27 granted patents·17 pending applications·773 citations·filing 2002–2014
97Inventor score
Top patents by PatentIndex Score
44 records- 0198US7569857B2Dual crystal orientation circuit devices on the same substrateINTEL CORP·Filed 2006·Granted Aug 4, 2009·119 cites·4 claims
- 0297US6908027B2Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening processINTEL CORP·Filed 2003·Granted Jun 21, 2005·224 cites·8 claims
- 0395US7573059B2Dislocation-free InSb quantum well structure on Si using novel buffer architectureINTEL CORP·Filed 2006·Granted Aug 11, 2009·41 cites·17 claims
- 0493US7042009B2High mobility tri-gate devices and methods of fabricationINTEL CORP·Filed 2004·Granted May 9, 2006·80 cites·9 claims
- 0592US7494911B2Buffer layers for device isolation of devices grown on siliconINTEL CORP·Filed 2006·Granted Feb 24, 2009·19 cites·15 claims
- 0692US7052978B2Arrangements incorporating laser-induced cleavingINTEL CORP·Filed 2003·Granted May 30, 2006·75 cites·38 claims
- 0791US6645831B1Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxideINTEL CORP·Filed 2002·Granted Nov 11, 2003·71 cites·25 claims
- 0890US7851780B2Semiconductor buffer architecture for III-V devices on silicon substratesINTEL CORP·Filed 2006·Granted Dec 14, 2010·14 cites·12 claims
- 0989US8143646B2Stacking fault and twin blocking barrier for integrating III-V on SiHUDAIT MANTU K·Filed 2006·Granted Mar 27, 2012·14 cites·16 claims
- 1085US8617945B2Stacking fault and twin blocking barrier for integrating III-V on SiHUDAIT MANTU K·Filed 2012·Granted Dec 31, 2013·6 cites·10 claims
- 1185US7161224B2Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening processINTEL CORP·Filed 2005·Granted Jan 9, 2007·12 cites·3 claims
- 1281US8735946B2Substrate having a charged zone in an insulating buried layerSOITEC SILICON ON INSULATOR·Filed 2013·Granted May 27, 2014·4 cites·16 claims
- 1379US6833195B1Low temperature germanium transferINTEL CORP·Filed 2003·Granted Dec 21, 2004·30 cites·26 claims
- 1476US8535996B2Substrate having a charged zone in an insulating buried layerSHAHEEN MOHAMAD·Filed 2008·Granted Sep 17, 2013·6 cites·11 claims
- 1572US7355247B2Silicon on diamond-like carbon devicesINTEL CORP·Filed 2005·Granted Apr 8, 2008·5 cites·18 claims
- 1668US7202503B2III-V and II-VI compounds as template materials for growing germanium containing film on siliconINTEL CORP·Filed 2004·Granted Apr 10, 2007·11 cites·14 claims
- 1764US7723749B2Strained semiconductor structuresINTEL CORP·Filed 2006·Granted May 25, 2010·1 cites·21 claims
- 1864US7148122B2Bonding of substratesINTEL CORP·Filed 2004·Granted Dec 12, 2006·9 cites·9 claims
- 1961US8084818B2High mobility tri-gate devices and methods of fabricationSHAHEEN MOHAMAD A·Filed 2006·Granted Dec 27, 2011·4 cites·8 claims
- 2061US7279369B2Germanium on insulator fabrication via epitaxial germanium bondingINTEL CORP·Filed 2003·Granted Oct 9, 2007·10 cites·37 claims
- 2160US7670928B2Ultra-thin oxide bonding for S1 to S1 dual orientation bondingINTEL CORP·Filed 2006·Granted Mar 2, 2010·1 cites·15 claims
- 2257US7851781B2Buffer layers for device isolation of devices grown on siliconINTEL CORP·Filed 2009·Granted Dec 14, 2010·0 cites·12 claims
- 2357US7473614B2Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layerINTEL CORP·Filed 2004·Granted Jan 6, 2009·6 cites·7 claims
- 2457US6911380B2Method of forming silicon on insulator wafersINTEL CORP·Filed 2002·Granted Jun 28, 2005·5 cites·21 claims
- 2553US2014225182A1Substrate having a charged zone in an insulating buried layerSOITEC SILICON ON INSULATOR·Filed 2014·Application pending·0 cites
- 2653US2010072580A1Ultra-thin oxide bonding for si to si dual orientation bondingINTEL CORP·Filed 2009·Application pending·0 cites
- 2751US2009096025A1Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layerTOLCHINSKY PETER G·Filed 2008·Application pending·0 cites
- 2850US8034675B2Semiconductor buffer architecture for III-V devices on silicon substratesINTEL CORP·Filed 2010·Granted Oct 11, 2011·0 cites·20 claims
- 2949US7378331B2Methods of vertically stacking wafers using porous siliconINTEL CORP·Filed 2004·Granted May 27, 2008·5 cites·30 claims
- 3048US7157379B2Strained semiconductor structuresINTEL CORP·Filed 2003·Granted Jan 2, 2007·1 cites·25 claims
- 3146US2006046488A1Germanium-on-insulator fabrication utilizing wafer bondingLEI RYAN·Filed 2005·Application pending·0 cites
- 3246US2006049399A1Germanium-on-insulator fabrication utilizing wafer bondingLEI RYAN·Filed 2005·Application pending·0 cites
- 3344US2007215984A1Formation of a multiple crystal orientation substrateSHAHEEN MOHAMAD A·Filed 2006·Application pending·0 cites
- 3442US2007238281A1Depositing polar materials on non-polar semiconductor substratesHUDAIT MANTU K·Filed 2006·Application pending·0 cites
- 3542US2006286771A1Layer transfer techniqueSHAHEEN MOHAMAD·Filed 2006·Application pending·0 cites
- 3642US2004106268A1Thermally stable crystalline defect-free germanium boned to silicon and silicon dioxideFiled 2003·Application pending·0 cites
- 3741US2010155788A1Formation of a multiple crystal orientation substrateSHAHEEN MOHAMAD A·Filed 2010·Application pending·0 cites
- 3840US2007063279A1Insulation layer for silicon-on-insulator waferTOLCHINSKY PETER G·Filed 2005·Application pending·0 cites
- 3939US2005217560A1Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the sameTOLCHINSKY PETER G·Filed 2004·Application pending·0 cites
- 4039US2005067377A1Germanium-on-insulator fabrication utilizing wafer bondingFiled 2003·Application pending·0 cites
- 4139US2005211982A1Strained silicon with reduced roughnessLEI RYAN·Filed 2004·Application pending·0 cites
- 4239US2008132081A1Thin III-V semiconductor films with high electron mobilitySHAHEEN MOHAMAD A·Filed 2006·Application pending·0 cites
- 4338US2004262686A1Layer transfer techniqueFiled 2003·Application pending·0 cites
- 4437US2005070048A1Devices and methods employing high thermal conductivity heat dissipation substratesFiled 2003·Application pending·0 cites
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