US2014225182A1PendingUtilityA1

Substrate having a charged zone in an insulating buried layer

Assignee: SOITEC SILICON ON INSULATORPriority: Mar 13, 2008Filed: Apr 15, 2014Published: Aug 14, 2014
Est. expiryMar 13, 2028(~1.6 yrs left)· nominal 20-yr term from priority
H10P 90/1918H10D 30/6758H10D 30/711H10D 62/53H10F 77/10H10B 12/01H01L 29/78603
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Claims

Abstract

A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 10 10 charges/cm 2 . Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 10 10 charges/cm 2 .

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A substrate, comprising:
 a base wafer;   an insulating layer over the base wafer, the insulating layer comprising a charge-confining layer confined on one or both sides with one or more diffusion barrier layers, the charge-confining layer having a density of charges in absolute value higher than 10 10  charges/cm 2 ; and   a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer.   
     
     
         2 . The substrate of  claim 1 , wherein the insulating layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, and a high k material. 
     
     
         3 . The substrate of  claim 1 , wherein the charge-confining layer comprises silicon nitride, and the one or more diffusion barrier layers includes at least one diffusion barrier layer comprising silicon oxide. 
     
     
         4 . The substrate of  claim 1 , wherein the charge-confining layer comprises silicon oxide, and the one or more diffusion barrier layers includes at least one diffusion barrier layer comprising silicon nitride. 
     
     
         5 . The substrate of  claim 1 , wherein the insulating layer comprises an oxide-nitride-oxide (ONO) structure. 
     
     
         6 . The substrate of  claim 1 , wherein the charges are at least partially provided by ions. 
     
     
         7 . The substrate of  claim 6 , wherein the charges are negative and the ions are selected from the group consisting of fluorine ions and chlorine ions. 
     
     
         8 . The substrate of  claim 6 , wherein the charges are positive and the ions are selected from the group consisting of boron ions and phosphorous ions. 
     
     
         9 . The substrate of  claim 1 , wherein the charge-confining layer comprises a doped charge-confining layer, and wherein the dopant is selected from the group consisting of boron, phosphorour, chlorine and fluorine. 
     
     
         10 . The substrate of  claim 1 , wherein the charge-confining layer has a thickness in a range extending from approximately 10 angstroms to approximately 1,000 angstroms. 
     
     
         11 . The substrate of  claim 1 , wherein each of the one or more diffusion barrier layers has a thickness in a range extending from approximately 10 angstroms to approximately 500 angstroms. 
     
     
         12 . The substrate of  claim 1 , wherein the charge-confining layer comprises ions uniformly dispersed therein. 
     
     
         13 . The substrate of  claim 1 , wherein the charge-confining layer comprises ions concentrated around a determined depth within the charge-confining layer. 
     
     
         14 . A substrate, comprising:
 a base wafer;   an insulating layer over the base wafer, the insulating layer comprising charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 10 1 ° charges/cm 2 ; and   a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer.   
     
     
         15 . The substrate of  claim 14 , wherein the charge-trapping islands comprise silicon. 
     
     
         16 . The substrate of  claim 14 , wherein the insulating layer has a thickness in a range extending from approximately 10 angstroms to approximately 5,000 angstroms. 
     
     
         17 . The substrate of  claim 14 , wherein the insulating layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, and a high k material. 
     
     
         18 . The substrate of  claim 14 , wherein the charges are at least partially provided by ions. 
     
     
         19 . The substrate of  claim 8 , wherein the charges are negative and the ions are selected from the group consisting of fluorine ions and chlorine ions. 
     
     
         20 . The substrate of  claim 14 , wherein the charges are at least partially provided by electrons.

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