Inventor · disambiguated record
Hartvig Ekner
Also filed as: EKNER HARTVIG · EKNER HARTVIG W J
16 granted patents·1 pending application·334 citations·filing 1996–2016
94Inventor score
Files withLSI LOGIC CORP6MIPS TECH INC5ALTERA CORP1ALTERA EUROP TRADING COMPANY LTD1APPLIED MICRO CIRCUITS CORP1
Top patents by PatentIndex Score
17 records- 0176US7984028B2System and method for application of hash function in telecommunication and networkingAPPLIED MICRO CIRCUITS CORP·Filed 2008·Granted Jul 19, 2011·9 cites·10 claims
- 0276US7237097B2Partial bitwise permutationsMIPS TECH INC·Filed 2001·Granted Jun 26, 2007·24 cites·36 claims
- 0375US6826681B2Instruction specified register value saving in allocated caller stack or not yet allocated callee stackMIPS TECH INC·Filed 2001·Granted Nov 30, 2004·16 cites·30 claims
- 0471US6412066B2Microprocessor employing branch instruction to set compression modeLSI LOGIC CORP·Filed 2001·Granted Jun 25, 2002·14 cites·23 claims
- 0569US7739484B2Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stackMIPS TECH INC·Filed 2007·Granted Jun 15, 2010·3 cites·9 claims
- 0669US6092159AImplementation of configurable on-chip fast memory using the data cache RAMLSI LOGIC CORP·Filed 1998·Granted Jul 18, 2000·58 cites·11 claims
- 0767US5867681AMicroprocessor having register dependent immediate decompressionLSI LOGIC CORP·Filed 1996·Granted Feb 2, 1999·52 cites·8 claims
- 0866US7281123B2Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offsetMIPS TECH INC·Filed 2004·Granted Oct 9, 2007·8 cites·22 claims
- 0966US6289445B2Circuit and method for initiating exception routines using implicit exception checkingLSI LOGIC CORP·Filed 1998·Granted Sep 11, 2001·48 cites·21 claims
- 1064US6189093B1System for initiating exception routine in response to memory access exception by storing exception information and exception bit within architectured registerLSI LOGIC CORP·Filed 1998·Granted Feb 13, 2001·49 cites·16 claims
- 1162US7599981B2Binary polynomial multiplierMIPS TECH INC·Filed 2001·Granted Oct 6, 2009·10 cites·39 claims
- 1262US5794010AMethod and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessorLSI LOGIC CORP·Filed 1996·Granted Aug 11, 1998·41 cites·20 claims
- 1360US8566487B2System and method for creating a scalable monolithic packet processing engineEKNER HARTVIG·Filed 2008·Granted Oct 22, 2013·2 cites·18 claims
- 1457US9807034B2System and method for creating a scalable monolithic packet processing engineALTERA CORP·Filed 2014·Granted Oct 31, 2017·0 cites·24 claims
- 1549US8868801B2System and method for creating a scalable monolithic packet processing engineALTERA EUROP TRADING COMPANY LTD·Filed 2013·Granted Oct 21, 2014·0 cites·17 claims
- 1644US10649486B1Apparatus and methods for accurate latency measurements in integrated circuitsINTEL CORP·Filed 2016·Granted May 12, 2020·0 cites·20 claims
- 1743US2001025337A1Microprocessor including a mode detector for setting compression modeFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →