Inventor · disambiguated record
Brian W. Thompto
Also filed as: THOMPTO BRIAN · THOMPTO BRIAN W · THOMPTO BRIAN WILLIAM
155 granted patents·18 pending applications·541 citations·filing 2004–2023
99Inventor score
Top patents by PatentIndex Score
173 records- 0197US11249757B1Handling and fusing load instructions in a processorIBM·Filed 2020·Granted Feb 15, 2022·6 cites·18 claims
- 0297US9720696B2Independent mapping of threadsIBM·Filed 2014·Granted Aug 1, 2017·30 cites·6 claims
- 0396US10037211B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2016·Granted Jul 31, 2018·15 cites·17 claims
- 0496US9672043B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 6, 2017·29 cites·8 claims
- 0595US11163571B1Fusion to enhance early address generation of load instructions in a microprocessorIBM·Filed 2020·Granted Nov 2, 2021·4 cites·20 claims
- 0695US9690586B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 27, 2017·26 cites·4 claims
- 0795US9665372B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted May 30, 2017·25 cites·16 claims
- 0895US7877580B2Branch lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Jan 25, 2011·41 cites·9 claims
- 0994US9690585B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted Jun 27, 2017·22 cites·9 claims
- 1093US10387147B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 20, 2019·7 cites·11 claims
- 1193US9870229B2Independent mapping of threadsIBM·Filed 2015·Granted Jan 16, 2018·8 cites·9 claims
- 1293US8521992B2Predicting and avoiding operand-store-compare hazards in out-of-order microprocessorsALEXANDER GREGORY W·Filed 2010·Granted Aug 27, 2013·21 cites·24 claims
- 1393US7395414B2Dynamic recalculation of resource vector at issue queue for steering of dependent instructionsIBM·Filed 2005·Granted Jul 1, 2008·31 cites·6 claims
- 1492US10671394B2Prefetch stream allocation for multithreading systemsIBM·Filed 2018·Granted Jun 2, 2020·9 cites·20 claims
- 1592US9977678B2Reconfigurable parallel execution and load-store slice processorIBM·Filed 2015·Granted May 22, 2018·7 cites·10 claims
- 1691US10042647B2Managing a divided load reorder queueIBM·Filed 2016·Granted Aug 7, 2018·6 cites·20 claims
- 1791US9934033B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 3, 2018·8 cites·11 claims
- 1890US11797713B2Systems and methods for dynamic control of a secure mode of operation in a processorIBM·Filed 2020·Granted Oct 24, 2023·2 cites·24 claims
- 1990US11520585B2Prefetch store preallocation in an effective address-based cache directoryIBM·Filed 2021·Granted Dec 6, 2022·2 cites·19 claims
- 2090US9971602B2Reconfigurable processing method with modes controlling the partitioning of clusters and cache slicesIBM·Filed 2015·Granted May 15, 2018·6 cites·5 claims
- 2190US9400657B2Dynamic management of a transaction retry indicationIBM·Filed 2013·Granted Jul 26, 2016·11 cites·12 claims
- 2289US9940133B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 10, 2018·6 cites·6 claims
- 2388US10223257B2Multi-section garbage collectionIBM·Filed 2015·Granted Mar 5, 2019·5 cites·13 claims
- 2488US9985656B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·7 cites·6 claims
- 2588US9483276B2Management of shared transactional resourcesIBM·Filed 2013·Granted Nov 1, 2016·8 cites·12 claims
- 2688US9298469B2Management of multiple nested transactionsBUSABA FADI Y·Filed 2012·Granted Mar 29, 2016·9 cites·20 claims
- 2787US11392386B2Program counter (PC)-relative load and store addressing for fused instructionsIBM·Filed 2020·Granted Jul 19, 2022·2 cites·20 claims
- 2887US7254697B2Method and apparatus for dynamic modification of microprocessor instruction group at dispatchIBM·Filed 2005·Granted Aug 7, 2007·18 cites·14 claims
- 2986US10394565B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 27, 2019·3 cites·6 claims
- 3086US10223125B2Linkable issue queue parallel execution slice processing methodIBM·Filed 2018·Granted Mar 5, 2019·3 cites·20 claims
- 3186US10083039B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Sep 25, 2018·3 cites·20 claims
- 3286US10078514B2Techniques for dynamic sequential instruction prefetchingIBM·Filed 2016·Granted Sep 18, 2018·4 cites·20 claims
- 3385US7594096B2Load lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Sep 22, 2009·13 cites·20 claims
- 3484US11900116B1Loosely-coupled slice target file dataIBM·Filed 2021·Granted Feb 13, 2024·1 cites·20 claims
- 3584US11868773B2Inferring future value for speculative branch resolution in a microprocessorIBM·Filed 2022·Granted Jan 9, 2024·1 cites·20 claims
- 3684US10671539B2Cache line replacement using reference states based on data reference attributesIBM·Filed 2018·Granted Jun 2, 2020·3 cites·20 claims
- 3784US9985655B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·6 cites·11 claims
- 3884US7254700B2Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flushIBM·Filed 2005·Granted Aug 7, 2007·14 cites·20 claims
- 3983US11531548B1Fast perfect issue of dependent instructions in a distributed issue queue systemIBM·Filed 2021·Granted Dec 20, 2022·1 cites·20 claims
- 4083US11132198B2Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2019·Granted Sep 28, 2021·2 cites·25 claims
- 4183US11119772B2Check pointing of accumulator register results in a microprocessorIBM·Filed 2019·Granted Sep 14, 2021·3 cites·18 claims
- 4283US9798549B1Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2016·Granted Oct 24, 2017·3 cites·13 claims
- 4383US9519479B2Techniques for increasing vector processing utilization and efficiency through vector lane predication predictionGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 13, 2016·7 cites·12 claims
- 4483US7631308B2Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessorsIBM·Filed 2005·Granted Dec 8, 2009·12 cites·3 claims
- 4582US10983800B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Apr 20, 2021·2 cites·20 claims
- 4682US10936321B2Instruction chainingIBM·Filed 2019·Granted Mar 2, 2021·3 cites·20 claims
- 4782US10073697B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2016·Granted Sep 11, 2018·2 cites·5 claims
- 4881US10157064B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2017·Granted Dec 18, 2018·2 cites·15 claims
- 4981US10133576B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Granted Nov 20, 2018·2 cites·18 claims
- 5080US12061909B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2023·Granted Aug 13, 2024·0 cites·21 claims
Showing the top 50 of 173 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →