Inventor · disambiguated record
See Chian Lim
Also filed as: LIM SEE C · LIM SEE CHIAN
6 granted patents·1 pending application·7 citations·filing 2005–2021
73Inventor score
Technology areasH10W
Top patents by PatentIndex Score
7 records- 0176US9240331B2Semiconductor device and method of making bumpless flipchip interconnect structuresSTATS CHIPPAC LTD·Filed 2013·Granted Jan 19, 2016·4 cites·22 claims
- 0270US9559039B2Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die packageSTATS CHIPPAC LTD·Filed 2013·Granted Jan 31, 2017·2 cites·19 claims
- 0368US12148677B2Semiconductor device and method of forming ultra high density embedded semiconductor die packageJCET SEMICONDUCTOR SHAOXING CO LTD·Filed 2021·Granted Nov 19, 2024·0 cites·20 claims
- 0461US9627338B2Semiconductor device and method of forming ultra high density embedded semiconductor die packageSTATS CHIPPAC LTD·Filed 2014·Granted Apr 18, 2017·1 cites·24 claims
- 0552US10242948B2Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die packageSTATS CHIPPAC PTE LTD·Filed 2016·Granted Mar 26, 2019·0 cites·24 claims
- 0650US11227809B2Semiconductor device and method of forming ultra high density embedded semiconductor die packageJCET SEMICONDUCTOR SHAOXING CO LTD·Filed 2017·Granted Jan 18, 2022·0 cites·25 claims
- 0734US2006160267A1Under bump metallurgy in integrated circuitsSTATS CHIPPAC LTD·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →