Inventor · disambiguated record
Alan Renninger
Also filed as: RENNINGER ALAN · RENNINGER ALAN L
11 granted patents·1 pending application·108 citations·filing 2000–2009
90Inventor score
Top patents by PatentIndex Score
12 records- 0186US7848151B2Circuit to control voltage ramp rateATMEL CORP·Filed 2009·Granted Dec 7, 2010·15 cites·18 claims
- 0286US7512008B2Circuit to control voltage ramp rateATMEL CORP·Filed 2005·Granted Mar 31, 2009·16 cites·12 claims
- 0381US7423912B2SONOS memory array with improved read disturb characteristicATMEL CORP·Filed 2006·Granted Sep 9, 2008·16 cites·8 claims
- 0476US6479351B1Method of fabricating a self-aligned non-volatile memory cellATMEL CORP·Filed 2000·Granted Nov 12, 2002·19 cites·12 claims
- 0574US7560334B2Method and system for incorporating high voltage devices in an EEPROMATMEL CORP·Filed 2005·Granted Jul 14, 2009·5 cites·25 claims
- 0670US6624027B1Ultra small thin windows in floating gate transistors defined by lost nitride spacersATMEL CORP·Filed 2002·Granted Sep 23, 2003·19 cites·12 claims
- 0760US6624029B2Method of fabricating a self-aligned non-volatile memory cellATMEL CORP·Filed 2002·Granted Sep 23, 2003·10 cites·12 claims
- 0859USRE40486ESelf-aligned non-volatile memory cellATMEL CORP·Filed 2005·Granted Sep 9, 2008·1 cites·6 claims
- 0957US6841823B2Self-aligned non-volatile memory cellATMEL CORP·Filed 2001·Granted Jan 11, 2005·6 cites·6 claims
- 1045US8093640B2Method and system for incorporating high voltage devices in an EEPROMSCHWANTES STEFAN·Filed 2009·Granted Jan 10, 2012·0 cites·21 claims
- 1144US2005189580A1Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cellATMEL CORP·Filed 2005·Application pending·0 cites
- 1240US7037786B2Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cellATMEL CORP·Filed 2003·Granted May 2, 2006·1 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →