Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cell

Abstract

A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step, thereby reducing the number of overall processing steps needed to form the devices.

1 . A non-volatile memory embedded logic circuit comprising: 
 a first device area, a second device area, and a third device area;    a first oxide layer on top of said second device area functioning as a gate oxide for a high voltage logic gate;    a second oxide layer that is thinner than said first oxide layer on top of said first and third device areas, whereby said second oxide layer on top of said first device area functions as a tunnel oxide while said second oxide layer on top of said third device area functions as a gate oxide for a low voltage logic gate; and    a floating gate layer overlying said first oxide layer.    
   
   
       2 . The circuit of  claim 1 , wherein said first oxide layer is approximately 250 Å thick.  
   
   
       3 . The non-volatile memory embedded logic circuit of  claim 1 , wherein said second oxide layer is approximately 70 Å thick.  
   
   
       4 . The non-volatile memory embedded logic circuit of  claim 1 , wherein said floating gate layer is a doped polysilicon layer.  
   
   
       5 . The non-volatile memory embedded logic circuit of  claim 1 , wherein said first oxide layer is formed in one processing step.  
   
   
       6 . The non-volatile memory embedded logic circuit of  claim 1 , wherein said second oxide layer is formed in one processing step.  
   
   
       7 . A non-volatile memory embedded logic circuit comprising: 
 a first device area and a second device area;    a first oxide layer on top of said second device area functioning as a gate oxide for a high voltage logic gate;    a second oxide layer that is thinner than said first oxide layer on top of said first device area, whereby said second oxide layer on top of said first device area functions as a tunnel oxide; and    a floating gate layer overlying said first oxide layer.    
   
   
       8 . The circuit of  claim 7 , wherein said first oxide layer is approximately 250 Å thick.  
   
   
       9 . The non-volatile memory embedded logic circuit of  claim 7 , wherein said second oxide layer is approximately 70 Åthick.