Inventor · disambiguated record
Stefan G. Block
Also filed as: BLOCK STEFAN · BLOCK STEFAN G
20 granted patents·4 pending applications·170 citations·filing 1999–2019
94Inventor score
Top patents by PatentIndex Score
24 records- 0187US6667703B1Matching calibration for digital-to-analog convertersLSI LOGIC CORP·Filed 2002·Granted Dec 23, 2003·40 cites·16 claims
- 0280US6567022B1Matching calibration for dual analog-to-digital convertersLSI CORP·Filed 2002·Granted May 20, 2003·27 cites·15 claims
- 0375US8219959B2Generating integrated circuit floorplan layoutsDIRKS JUERGEN·Filed 2009·Granted Jul 10, 2012·7 cites·17 claims
- 0474US11329129B2Transistor cell for integrated circuits and method to form sameGLOBALFOUNDRIES US INC·Filed 2019·Granted May 10, 2022·2 cites·13 claims
- 0574US9773811B2Reducing antenna effects in SOI devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 26, 2017·3 cites·20 claims
- 0674US7829973B2N cell height decoupling circuitLSI CORP·Filed 2007·Granted Nov 9, 2010·9 cites·20 claims
- 0773US7650548B2Power saving flip-flopLSI CORP·Filed 2007·Granted Jan 19, 2010·7 cites·19 claims
- 0867US10505545B1Simplified bias scheme for digital designsGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 10, 2019·1 cites·20 claims
- 0966US7514974B2Method and apparatus for adjusting on-chip delay with power supply controlLSI CORP·Filed 2007·Granted Apr 7, 2009·6 cites·18 claims
- 1063US10114919B2Placing and routing method for implementing back bias in FDSOIGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 30, 2018·1 cites·19 claims
- 1163US7944237B2Adjustable hold flip flop and method for adjusting hold requirementsLSI CORP·Filed 2010·Granted May 17, 2011·1 cites·18 claims
- 1263US7088158B2Digital multi-phase clock generatorLSI LOGIC CORP·Filed 2002·Granted Aug 8, 2006·13 cites·18 claims
- 1362US6313683B1Method of providing clock signals to load circuits in an ASIC deviceLSI LOGIC CORP·Filed 1999·Granted Nov 6, 2001·26 cites·21 claims
- 1461US7616517B1Config logic power saving methodLSI CORP·Filed 2008·Granted Nov 10, 2009·2 cites·14 claims
- 1558US6756832B2Digitally-programmable delay line for multi-phase clock generatorLSI LOGIC CORP·Filed 2002·Granted Jun 29, 2004·10 cites·17 claims
- 1656US8564337B2Clock tree insertion delay independent interfaceBLOCK STEFAN·Filed 2011·Granted Oct 22, 2013·1 cites·20 claims
- 1755US7880498B2Adjustable hold flip flop and method for adjusting hold requirementsLSI CORP·Filed 2007·Granted Feb 1, 2011·2 cites·12 claims
- 1855US6904554B2Logic built-in self test (BIST)LSI LOGIC CORP·Filed 2002·Granted Jun 7, 2005·10 cites·21 claims
- 1949US11450753B2Edge cell signal line antenna diodesGLOBALFOUNDRIES US INC·Filed 2019·Granted Sep 20, 2022·0 cites·20 claims
- 2049US8078926B2Test pin gating for dynamic optimizationBLOCK STEFAN G·Filed 2009·Granted Dec 13, 2011·2 cites·6 claims
- 2136US2011320997A1Delay-Cell Footprint-Compatible BuffersLABIB FARID·Filed 2010·Application pending·0 cites
- 2236US2014281284A1Multi-read port memoryLSI CORP·Filed 2013·Application pending·0 cites
- 2331US2011063926A1Write Through Speed Up for Memory CircuitLSI CORP·Filed 2009·Application pending·0 cites
- 2431US2016284392A1Memory cell, memory device including a plurality of memory cells and method including read and write operations at a memory cellGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →