Inventor · disambiguated record
Suresh K. Venkumahanti
Also filed as: VENKUMAHANTI SURESH · VENKUMAHANTI SURESH K · VENKUMAHANTI SURESH KUMAR
49 granted patents·13 pending applications·228 citations·filing 2002–2024
97Inventor score
Top patents by PatentIndex Score
62 records- 0190US8341353B2System and method to access a portion of a level two memory and a level one memoryVENKUMAHANTI SURESH K·Filed 2010·Granted Dec 25, 2012·15 cites·27 claims
- 0288US8397238B2Thread allocation and clock cycle adjustment in an interleaved multi-threaded processorVENKUMAHANTI SURESH K·Filed 2009·Granted Mar 12, 2013·19 cites·39 claims
- 0387US6785772B2Data prefetching apparatus in a data processing system and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Aug 31, 2004·47 cites·21 claims
- 0486US8140823B2Multithreaded processor with lock indicatorCODRESCU LUCIAN·Filed 2007·Granted Mar 20, 2012·16 cites·29 claims
- 0585US8370806B2Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processorQUALCOMM INC·Filed 2006·Granted Feb 5, 2013·17 cites·24 claims
- 0684US8341604B2Embedded trace macrocell for enhanced digital signal processor debugging operationsCODRESCU LUCIAN·Filed 2006·Granted Dec 25, 2012·16 cites·37 claims
- 0782US7657791B2Method and system for a digital signal processor debugging during power transitionsQUALCOMM INC·Filed 2006·Granted Feb 2, 2010·13 cites·32 claims
- 0881US10625752B2System and method for online functional testing for error-correcting code functionQUALCOMM INC·Filed 2017·Granted Apr 21, 2020·3 cites·22 claims
- 0980US8145874B2System and method of data forwarding within an execution unitVENKUMAHANTI SURESH·Filed 2008·Granted Mar 27, 2012·13 cites·27 claims
- 1079US9384825B2Multi-port memory circuitsQUALCOMM INC·Filed 2014·Granted Jul 5, 2016·6 cites·20 claims
- 1176US9489204B2Method and apparatus for precalculating a direct branch partial target address during a misprediction correction processQUALCOMM INC·Filed 2013·Granted Nov 8, 2016·4 cites·30 claims
- 1276US8380966B2Method and system for instruction stuffing operations during non-intrusive digital signal processor debuggingQUALCOMM INC·Filed 2006·Granted Feb 19, 2013·8 cites·35 claims
- 1375US8972642B2Low latency two-level interrupt controller interface to multi-threaded processorVENKUMAHANTI SURESH K·Filed 2011·Granted Mar 3, 2015·4 cites·29 claims
- 1475US7827356B2System and method of using an N-way cacheQUALCOMM INC·Filed 2007·Granted Nov 2, 2010·6 cites·30 claims
- 1574US9122486B2Bimodal branch predictor encoded in a branch instructionVENKUMAHANTI SURESH K·Filed 2010·Granted Sep 1, 2015·5 cites·22 claims
- 1673US11200058B2Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable mediaQUALCOMM INC·Filed 2014·Granted Dec 14, 2021·4 cites·24 claims
- 1770US8725991B2Register file system and method for pipelined processingWANG LIN·Filed 2007·Granted May 13, 2014·6 cites·8 claims
- 1868US9367468B2Data cache way predictionQUALCOMM INC·Filed 2013·Granted Jun 14, 2016·2 cites·29 claims
- 1967US9804969B2Speculative addressing using a virtual address-to-physical address page crossing bufferQUALCOMM INC·Filed 2012·Granted Oct 31, 2017·2 cites·24 claims
- 2067US9116685B2Table call instruction for frequently called functionsPLONDKE ERICH JAMES·Filed 2011·Granted Aug 25, 2015·2 cites·23 claims
- 2165US8990543B2System and method for generating and using predicates within a single instruction packetCODRESCU LUCIAN·Filed 2008·Granted Mar 24, 2015·3 cites·34 claims
- 2265US8874884B2Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than thresholdVENKUMAHANTI SURESH K·Filed 2011·Granted Oct 28, 2014·2 cites·16 claims
- 2364US9715392B2Multiple clustered very long instruction word processing coreQUALCOMM INC·Filed 2014·Granted Jul 25, 2017·2 cites·24 claims
- 2464US7979681B2System and method of selectively accessing a register fileQUALCOMM INC·Filed 2007·Granted Jul 12, 2011·3 cites·21 claims
- 2563US9678758B2Coprocessor for out-of-order loadsQUALCOMM INC·Filed 2014·Granted Jun 13, 2017·1 cites·19 claims
- 2662US10025711B2Hybrid write-through/write-back cache policy managers, and related systems and methodsSASSONE PETER G·Filed 2012·Granted Jul 17, 2018·2 cites·28 claims
- 2761US11663011B2System and method of VLIW instruction processing using reduced-width VLIW processorQUALCOMM INC·Filed 2020·Granted May 30, 2023·0 cites·20 claims
- 2861US7984281B2Shared interrupt controller for a multi-threaded processorQUALCOMM INC·Filed 2007·Granted Jul 19, 2011·2 cites·3 claims
- 2958US9208102B2Overlap checking for a translation lookaside buffer (TLB)QUALCOMM INC·Filed 2013·Granted Dec 8, 2015·1 cites·21 claims
- 3058US8533530B2Method and system for trusted/untrusted digital signal processor debugging operationsCODRESCU LUCIAN·Filed 2006·Granted Sep 10, 2013·1 cites·30 claims
- 3156US8868888B2System and method of executing instructions in a multi-stage data processing pipelineINGLE AJAY ANANT·Filed 2007·Granted Oct 21, 2014·1 cites·38 claims
- 3255US10719325B2System and method of VLIW instruction processing using reduced-width VLIW processorQUALCOMM INC·Filed 2017·Granted Jul 21, 2020·0 cites·20 claims
- 3354US12450060B1Sharing loop cache instances among multiple threads in processor devicesQUALCOMM INC·Filed 2024·Granted Oct 21, 2025·0 cites·20 claims
- 3452US7941646B2Completion continue on thread switch based on instruction progress metric mechanism for a microprocessorFREESCALE SEMICONDOCTOR INC·Filed 2007·Granted May 10, 2011·1 cites·20 claims
- 3551US9529727B2Reconfigurable fetch pipelineQUALCOMM INC·Filed 2014·Granted Dec 27, 2016·0 cites·24 claims
- 3651US2025165143A1System and method for reducing memory footprint for data stored in a compressed memory subsystemQUALCOMM INC·Filed 2023·Application pending·0 cites
- 3750US8578382B2Associating data for events occurring in software threads with synchronized clock cycle countersVENKUMAHANTI SURESH K·Filed 2009·Granted Nov 5, 2013·1 cites·31 claims
- 3849US10007613B2Reconfigurable fetch pipelineQUALCOMM INC·Filed 2016·Granted Jun 26, 2018·0 cites·30 claims
- 3949US9304932B2Instruction cache having a multi-bit way prediction maskQUALCOMM INC·Filed 2012·Granted Apr 5, 2016·0 cites·24 claims
- 4048US10055227B2Using the least significant bits of a called function's address to switch processor modesQUALCOMM INC·Filed 2012·Granted Aug 21, 2018·0 cites·23 claims
- 4148US2009327674A1Loop Control System and MethodQUALCOMM INC·Filed 2008·Application pending·0 cites
- 4247US2025156187A1Reduction of data transfer overheadQUALCOMM INC·Filed 2023·Application pending·0 cites
- 4347US2012284488A1Methods and Apparatus for Constant Extension in a ProcessorPLONDKE ERICH JAMES·Filed 2011·Application pending·0 cites
- 4447US2012284489A1Methods and Apparatus for Constant Extension in a ProcessorPLONDKE ERICH JAMES·Filed 2011·Application pending·0 cites
- 4546US9824013B2Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processorsKOOB CHRISTOPHER EDWARD·Filed 2012·Granted Nov 21, 2017·0 cites·20 claims
- 4646US9552033B2Latency-based power mode units for controlling power modes of processor cores, and related methods and systemsQUALCOMM INC·Filed 2014·Granted Jan 24, 2017·0 cites·30 claims
- 4745US11599625B2Techniques for instruction perturbation for improved device securityQUALCOMM INC·Filed 2021·Granted Mar 7, 2023·0 cites·20 claims
- 4845US9928159B2System and method to select a packet format based on a number of executed threadsQUALCOMM INC·Filed 2013·Granted Mar 27, 2018·0 cites·31 claims
- 4945US9361109B2System and method to evaluate a data value as an instructionCODRESCU LUCIAN·Filed 2010·Granted Jun 7, 2016·0 cites·48 claims
- 5045US8880958B2Interleaved architecture tracing and microarchitecture tracingVENKUMAHANTI SURESH K·Filed 2011·Granted Nov 4, 2014·0 cites·24 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →