Loop Control System and Method

Abstract

Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.

1 . A method of processing a set of instructions in a loop, the method comprising:
 automatically initializing a predicate trigger counter to indicate a number of iterations of the loop before setting a predicate value upon execution of a particular type of loop instruction;   executing the set of instructions during a loop iteration; and   upon detecting an end of loop indicator of the loop, automatically triggering loop control hardware to modify the predicate trigger counter and to compare the predicate trigger counter to a reference to determine when to set the predicate value and wherein at least one of the instructions in the set of instructions is conditionally executed based on the predicate value.   
   
   
       2 . The method of  claim 1 , wherein the reference is a zero value and wherein the loop control hardware decrements the predicate trigger counter in response to the end of loop indicator. 
   
   
       3 . The method of  claim 1 , wherein the at least one of the instructions in the set of instructions that is conditionally executed writes data to an output register. 
   
   
       4 . The method of  claim 3 , wherein the set of instructions is executed as a software pipelined loop, and wherein the predicated trigger counter is based on a number of pipeline stages of the software pipelined loop. 
   
   
       5 . A method of processing loop instructions, the method comprising:
 initializing loop parameters in special registers including a predicate trigger count;   executing the loop instructions;   executing an instruction with an end of loop indicator;   modifying the predicate trigger count and modifying a loop count; and   when the predicate trigger count equals a reference value, changing a value of a predicate that affects execution of at least one of the loop instructions.   
   
   
       6 . The method of  claim 5 , wherein the loop instructions include kernel code but the loop instructions do not include prolog instructions. 
   
   
       7 . The method of  claim 6 , wherein the kernel code comprises a set of instructions of a software pipelined loop. 
   
   
       8 . The method of  claim 5 , wherein the reference value equals zero, and wherein the predicate trigger count and the loop count are decremented in response to executing the instruction with the end of loop indicator. 
   
   
       9 . The method of  claim 5 , wherein the loop instructions include at least one instruction that is conditionally executed based on the predicate. 
   
   
       10 . The method of  claim 9 , wherein the loop instructions include kernel code but the loop instructions do not include prolog instructions. 
   
   
       11 . An apparatus comprising:
 a predicate count register to store a predicate trigger count;   an initialization logic circuit to initialize loop parameters of a program loop;   a processor to execute loop instructions of the program loop and to execute a packet including an end of loop indicator;   a logic circuit to modify the predicate trigger count and to modify a loop count of the program loop;   a comparison logic circuit to compare the predicate trigger count to a reference value; and   a logic circuit to change a value of a predicate that affects at least one instruction in the program loop based on a result of the comparison.   
   
   
       12 . The apparatus of  claim 11 , wherein the initialization logic circuit clears the predicate prior to execution of the loop instructions. 
   
   
       13 . A hardware loop control logic circuit comprising:
 a detection unit to detect an end of loop indicator of a program loop;   a decrement unit to decrement a loop count and to decrement a predicate trigger counter; and   a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.   
   
   
       14 . The hardware loop control logic circuit of  claim 13 , wherein the program loop includes at least one instruction that is conditionally executable based on the predicate value. 
   
   
       15 . A system comprising:
 a hardware loop control logic circuit comprising:
 a detection unit to detect an end of loop indicator of a program loop; 
 a decrement unit to decrement a loop count and to decrement a predicate trigger counter; and 
 a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value; and 
   a processor that executes a special instruction that triggers execution of the hardware loop control logic circuit.   
   
   
       16 . The system of  claim 15 , wherein the special instruction comprises an spNloop type instruction where N is a positive integer less than four and where N indicates the number of loops of the program loop to execute before changing the predicate value. 
   
   
       17 . The system of  claim 16 , wherein upon execution of the spNloop type instruction, values are calculated prior to the predicate value being set and the calculated values are not stored. 
   
   
       18 . The system of  claim 16 , wherein the spNloop type instruction includes a data field that includes program loop setup information. 
   
   
       19 . The system of  claim 18 , wherein the detection unit is configured to parse a very long instruction word (VLIW) packet to detect the end of loop indicator, wherein the decrement unit includes a counter to automatically decrement the predicate trigger counter when the end of loop indicator is detected, and wherein the comparison unit includes a comparator to automatically identify a transition from a one value to a zero value of the predicate trigger counter. 
   
   
       20 . The system of  claim 16 , wherein the spNloop type instruction is used in connection with a software pipeline loop application. 
   
   
       21 . The system of  claim 17 , wherein the processor is a very long instruction word (VLIW) type processor that includes the hardware loop control logic circuit and wherein multiple instructions in the program loop are executed in parallel by the processor. 
   
   
       22 . The system of  claim 18 , wherein N identifies a prolog count. 
   
   
       23 . The system of  claim 16 , wherein at least one instruction of the program loop conditionally stores data based on the predicate value.