Inventor · disambiguated record
Rustom Irani
Also filed as: IRANI RUSTOM · IRANI RUSTOM F
12 granted patents·7 pending applications·205 citations·filing 1990–2010
92Inventor score
Files withSAIFUN SEMICONDUCTORS LTD6WAFERSCALE INTEGRATION INC5EITAN BOAZ3IRANI RUSTOM3ST MICROELECTRONICS SRL1
Top patents by PatentIndex Score
19 records- 0190US7811887B2Forming silicon trench isolation (STI) in semiconductor devices self-aligned to diffusionSAIFUN SEMICONDUCTORS LTD·Filed 2007·Granted Oct 12, 2010·19 cites·7 claims
- 0289US7638835B2Double density NROM with nitride strips (DDNS)SAIFUN SEMICONDUCTORS LTD·Filed 2006·Granted Dec 29, 2009·16 cites·3 claims
- 0387US7786512B2Dense non-volatile memory array and method of fabricationSAIFUN SEMICONDUCTORS LTD·Filed 2006·Granted Aug 31, 2010·10 cites·20 claims
- 0483US7804126B2Dense non-volatile memory array and method of fabricationSAIFUN SEMICONDUCTORS LTD·Filed 2006·Granted Sep 28, 2010·7 cites·6 claims
- 0581US7638850B2Non-volatile memory structure and method of fabricationSAIFUN SEMICONDUCTORS LTD·Filed 2006·Granted Dec 29, 2009·6 cites·7 claims
- 0679US5683925AManufacturing method for ROM array with minimal band-to-band tunnelingWAFERSCALE INTEGRATION INC·Filed 1996·Granted Nov 4, 1997·62 cites·9 claims
- 0777US7964459B2Non-volatile memory structure and method of fabricationSpansion Israel Ltd·Filed 2009·Granted Jun 21, 2011·4 cites·14 claims
- 0872US5151375AEPROM virtual ground arrayWAFERSCALE INTEGRATION INC·Filed 1990·Granted Sep 29, 1992·48 cites·8 claims
- 0962US5910016AScalable EPROM arrayWAFERSCALE INTEGRATION INC·Filed 1997·Granted Jun 8, 1999·18 cites·4 claims
- 1050US2008266954A1Transition areas for dense memory arraysEITAN BOAZ·Filed 2008·Application pending·0 cites
- 1149US6300195B1Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual groundST MICROELECTRONICS SRL·Filed 2000·Granted Oct 9, 2001·5 cites·15 claims
- 1249US2008239807A1Transition areas for dense memory arraysEITAN BOAZ·Filed 2008·Application pending·0 cites
- 1347US2007120180A1Transition areas for dense memory arraysEITAN BOAZ·Filed 2006·Application pending·0 cites
- 1446US2006261418A1Memory cell with double bb implantSAIFUN SEMICONDUCTORS LTD·Filed 2006·Application pending·0 cites
- 1544US2008111182A1Forming buried contact etch stop layer (CESL) in semiconductor devices self-aligned to diffusionIRANI RUSTOM·Filed 2007·Application pending·0 cites
- 1644US2011057241A1Forming silicon trench isolation (sti) in semiconductor devices self-aligned to diffusionIRANI RUSTOM·Filed 2010·Application pending·0 cites
- 1743US2008025084A1High aspect ration bitline oxidesIRANI RUSTOM·Filed 2007·Application pending·0 cites
- 1839US5623443AScalable EPROM array with thick and thin non-field oxide gate insulatorsWAFERSCALE INTEGRATION INC·Filed 1994·Granted Apr 22, 1997·6 cites·6 claims
- 1933US5838046AOperating method for ROM array which minimizes band-to-band tunnelingWAFERSCALE INTEGRATION INC·Filed 1996·Granted Nov 17, 1998·4 cites·2 claims
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