Forming silicon trench isolation (sti) in semiconductor devices self-aligned to diffusion

Abstract

Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices.

What is claimed is: 
     
         1 . An array of memory cells comprising:
 a plurality of bitlines extending through a contact area in the array;   silicon trench isolation (STI) trenches disposed in the contact area, and self-aligned between adjacent bitlines;   memory devices connected between the bitlines in a cell area adjacent to the contact area;   inter-level dielectric covering the memory devices and filling the STI trenches; and   said STI trenches of the STI are lined with a CMOS spacer.   
     
     
         2 . The array of  claim 1 , wherein:
 the bitlines are composed of material selected from the group consisting of silicides, metals, raised diffusions or buried bitlines.   
     
     
         3 . The array of  claim 1 , wherein:
 the STI trenches of the STI are lines with a salicide blocking layer.   
     
     
         4 . The array of  claim 1 , wherein:
 the STI trenches of the STI are lined with a contact etch stop layer.   
     
     
         5 . The array of  claim 1 , wherein:
 the STI trenches of the STI are lined with a salicide blocking layer and a contact etch stop layer.   
     
     
         6 . The array of  claim 1 , wherein:
 the memory cells comprise NVM devices.   
     
     
         7 . The array of  claim 6 , wherein:
 the NVM devices are selected from the group consisting of NROM, SONOS, SANOS, MANOS, TANOS and Floating Gate (FG) devices.