Inventor · disambiguated record
Paolo Caprara
Also filed as: CAPRARA PAOLO
14 granted patents·1 pending application·115 citations·filing 1993–2006
92Inventor score
Top patents by PatentIndex Score
15 records- 0184US6825523B2Process for manufacturing a dual charge storage location memory cellST MICROELECTRONICS SRL·Filed 2002·Granted Nov 30, 2004·34 cites·27 claims
- 0262US5440510AIntegrated circuit entirely protected against ultraviolet raysSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Aug 8, 1995·21 cites·30 claims
- 0356US6365456B1Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual groundST MICROELECTRONICS SRL·Filed 2000·Granted Apr 2, 2002·6 cites·16 claims
- 0455US6700226B2Multi-emitter bipolar transistor for bandgap reference circuitsSTMICROELECTRONIC S R L·Filed 2001·Granted Mar 2, 2004·7 cites·8 claims
- 0550US6063663AMethod for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memoriesSGS THOMSON MICROELECTRONICS·Filed 1998·Granted May 16, 2000·12 cites·7 claims
- 0649US6350671B1Method for autoaligning overlapped lines of a conductive material in integrated electronic circuitsST MICROELECTRONICS SRL·Filed 2000·Granted Feb 26, 2002·4 cites·11 claims
- 0749US6300195B1Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual groundST MICROELECTRONICS SRL·Filed 2000·Granted Oct 9, 2001·5 cites·15 claims
- 0845US7319604B2Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cellST MICROELECTRONICS SRL·Filed 2005·Granted Jan 15, 2008·1 cites·31 claims
- 0945US7115472B2Process for manufacturing a dual charge storage location memory cellST MICROELECTRONICS SRL·Filed 2004·Granted Oct 3, 2006·2 cites·20 claims
- 1040US6326266B1Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrixST MICROELECTRONICS SRL·Filed 1998·Granted Dec 4, 2001·7 cites·10 claims
- 1138US7091570B2MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contactST MICROELECTRONICS SRL·Filed 2003·Granted Aug 15, 2006·2 cites·14 claims
- 1237US7023047B2MOS device and process for manufacturing MOS devices using dual-polysilicon layer technologyST MICROELECTRONICS SRL·Filed 2003·Granted Apr 4, 2006·2 cites·20 claims
- 1337US6251736B1Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arraysST MICROELECTRONICS SRL·Filed 1999·Granted Jun 26, 2001·7 cites·15 claims
- 1437US2006246646A1MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contactST MICROELECTRONICS SRL·Filed 2006·Application pending·0 cites
- 1533US6124169AContact structure and associated process for production of semiconductor electronic devices and in particular nonvolatile EPROM and flash EPROM memoriesST MICROELECTRONICS SRL·Filed 1997·Granted Sep 26, 2000·5 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →