MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact

Abstract

A process for manufacturing a MOS device is described. The process comprising: providing a body of semiconductor material having a surface; forming a stack on the surface of the body, the stack including a first polysilicon region, an intermediate dielectric region arranged on top of the first polysilicon region, and a second polysilicon region arranged on top of the intermediate dielectric region; depositing a passivation layer on top of and laterally to the stack; and forming at least one electrical connection region in direct electrical contact with the first and second polysilicon regions, wherein the electrical connection region is formed laterally with respect to both the first and second polysilicon regions.

1 . A process for manufacturing a MOS device comprising: 
 providing a body of semiconductor material having a surface;    forming a stack on said surface of said body, said stack including a first polysilicon region, an intermediate dielectric region arranged on top of said first polysilicon region, and a second polysilicon region arranged on top of said intermediate dielectric region;    depositing a passivation layer on top of and laterally to said stack; and    forming at least one electrical connection region in direct electrical contact with said first and second polysilicon regions, wherein said electrical connection region is formed laterally with respect to both said first and second polysilicon regions.    
   
   
       2 . The process according to  claim 1  wherein said electrical connection region extends substantially as far as said surface of said body.  
   
   
       3 . The process according to  claim 1  wherein said step of forming at least one electrical connection region comprises the steps of: 
 forming a contact mask;    forming, using said contact mask, at least one via extending in said passivation layer laterally with respect to said first and second polysilicon regions and with respect to said intermediate dielectric region; and    filling said via with conductive material.    
   
   
       4 . The process according to  claim 3  wherein said step of filling comprises depositing a barrier layer on walls and on the bottom of said via and filling said via with metal material.  
   
   
       5 . The process according to  claim 1  wherein said step of forming a stack comprises forming a gate region of a MOS transistor.  
   
   
       6 . The process according to  claim 5 , further comprising, prior to said step of forming a stack, forming, in said body, a field insulation region delimiting an active area, wherein said step of forming a gate region comprises forming an elongated structure having a central portion extending on top of said active area and end portions extending on top of said field insulation region, and wherein said electrical connection region is formed on top of said field insulation region.  
   
   
       7 . The process according to  claim 6  wherein said step of forming at least one electrical connection region comprises the steps of: 
 forming a contact mask;    forming, using said contact mask, a plurality of vias extending in said passivation layer, said plurality of vias including at least one first via extending laterally with respect to said first and second polysilicon regions and to said intermediate dielectric region, and second vias extending as far as conductive regions inside said active area; and    filling said plurality of vias with conductive material.    
   
   
       8 . A process comprising: 
 providing a body of semiconductor material having a surface;    forming a stack on top of said body, said stack having a top surface, a bottom surface, first, second, third and forth side, said bottom surface being in contact with said surface of said semiconductor material, said stack comprising a first polysilicon region, an intermediate dielectric region being arranged on top of said first polysilicon region, and a second polysilicon region being arranged on top of said intermediate dielectric region;    depositing a passivation layer on top of and laterally to said stack and said semiconductor body; and    forming at least one electrical connection region in direct electrical contact with said first and second polysilicon regions and said electrical connection region extending through said passivation layer and further extending substantially as far as said surface of said semiconductor body.    
   
   
       9 . The process according to  claim 8  wherein the electrical connection region is in contact with first and second polysilicon region by contacting said first side of the stack.  
   
   
       10 . The process according to  claim 8  wherein at least part of the electrical connection region terminates on the top surface of said stack and present a step.  
   
   
       11 . A process for manufacturing a MOS device comprising: 
 forming a field insulation region and an active area in a semiconductor substrate;    forming a stack overlying the semiconductor substrate, the stack having a top surface and lateral sides, a central portion of the stack extending on top of the active area and an end portion of the stack extending on top of the field insulation region, the stack including a first polysilicon region, an intermediate dielectric region and a second polysilicon;    covering the top surface and lateral sides of the stack with a passivation layer;    forming a contact mask on top of the passivation layer, the contact mask defining an opening;    etching a via defined by the opening to extend through an entire height of the passivation layer and laterally with respect to the stack; and    forming a electrical connection region in the via, the electrical connection region being in electrical contact with the first polysilicon region and the second polysilicon region.    
   
   
       12 . The process of  claim 11  wherein the electrical connection region extends substantially to the field insulation region of the semiconductor substrate.  
   
   
       13 . The process of  claim 11  further comprising forming a barrier layer in the via.  
   
   
       14 . The process of  claim 11  wherein a portion of the electrical connection region terminates on the top surface of the stack.