Inventor · disambiguated record
Dominic J. Schepis
Also filed as: SCHEPIS DOMINIC · SCHEPIS DOMINIC J · SCHEPIS DOMINIC JOSEPH
141 granted patents·19 pending applications·3,012 citations·filing 1982–2020
99Inventor score
Top patents by PatentIndex Score
160 records- 0198US9812575B1Contact formation for stacked FinFETsGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 7, 2017·25 cites·17 claims
- 0298US9514995B1Implant-free punch through doping layer formation for bulk FinFET structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 6, 2016·22 cites·7 claims
- 0398US9368512B1Double diamond shaped unmerged epitaxy for tall fins in tight pitchIBM·Filed 2015·Granted Jun 14, 2016·24 cites·20 claims
- 0498US7622341B2Sige channel epitaxial development for high-k PFET manufacturabilityIBM·Filed 2008·Granted Nov 24, 2009·121 cites·21 claims
- 0598US7544994B2Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structureIBM·Filed 2006·Granted Jun 9, 2009·61 cites·21 claims
- 0698US6717216B1SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the deviceIBM·Filed 2002·Granted Apr 6, 2004·282 cites·15 claims
- 0797US6214694B1Process of making densely patterned silicon-on-insulator (SOI) region on a waferIBM·Filed 1998·Granted Apr 10, 2001·244 cites·17 claims
- 0896US9634142B1Method for improving boron diffusion in a germanium-rich fin through germanium concentration reduction in fin S/D regions by thermal mixingGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 25, 2017·17 cites·14 claims
- 0996US9443873B1Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy stepIBM·Filed 2015·Granted Sep 13, 2016·11 cites·20 claims
- 1096US9385023B1Method and structure to make fins with different fin heights and no topographyGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 5, 2016·14 cites·13 claims
- 1196US8999779B2Locally raised epitaxy for improved contact by local silicon capping during trench silicide processingsIBM·Filed 2013·Granted Apr 7, 2015·23 cites·8 claims
- 1296US7781273B2Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structureIBM·Filed 2008·Granted Aug 24, 2010·34 cites·3 claims
- 1395US7381623B1Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performanceIBM·Filed 2007·Granted Jun 3, 2008·31 cites·16 claims
- 1495US6288426B1Thermal conductivity enhanced semiconductor structures and fabrication processesIBM·Filed 2000·Granted Sep 11, 2001·87 cites·32 claims
- 1594US9305883B2Locally raised epitaxy for improved contact by local silicon capping during trench silicide processingsGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 5, 2016·10 cites·11 claims
- 1694US9224811B2Stacked semiconductor deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 29, 2015·18 cites·7 claims
- 1794US7781800B2Embedded silicon germanium using a double buried oxide silicon-on-insulator waferIBM·Filed 2008·Granted Aug 24, 2010·24 cites·17 claims
- 1893US9525027B2Lateral bipolar junction transistor having graded SiGe baseGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 20, 2016·13 cites·14 claims
- 1993US9450079B2FinFET having highly doped source and drain regionsIBM·Filed 2014·Granted Sep 20, 2016·10 cites·10 claims
- 2093US6531375B1Method of forming a body contact using BOX modificationIBM·Filed 2001·Granted Mar 11, 2003·78 cites·13 claims
- 2193US6291858B1Multistack 3-dimensional high density semiconductor device and method for fabricationIBM·Filed 2000·Granted Sep 18, 2001·74 cites·9 claims
- 2293US4960726ABiCMOS processIBM·Filed 1989·Granted Oct 2, 1990·78 cites·10 claims
- 2392US9343550B2Silicon-on-nothing FinFETsGLOBALFOUNDRIES INC·Filed 2015·Granted May 17, 2016·6 cites·17 claims
- 2492US9041062B2Silicon-on-nothing FinFETsIBM·Filed 2013·Granted May 26, 2015·9 cites·20 claims
- 2592US8361859B2Stressed transistor with improved metastabilityIBM·Filed 2010·Granted Jan 29, 2013·13 cites·15 claims
- 2692US6429084B1MOS transistors with raised sources and drainsIBM·Filed 2001·Granted Aug 6, 2002·73 cites·11 claims
- 2792US4758531AMethod of making defect free silicon islands using SEGIBM·Filed 1987·Granted Jul 19, 1988·100 cites·16 claims
- 2891US8575655B2Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineeringBEDELL STEPHEN W·Filed 2012·Granted Nov 5, 2013·9 cites·19 claims
- 2990US9647119B1Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy stepIBM·Filed 2016·Granted May 9, 2017·4 cites·6 claims
- 3089US9935181B2FinFET having highly doped source and drain regionsIBM·Filed 2015·Granted Apr 3, 2018·4 cites·10 claims
- 3189US9728626B1Almost defect-free active channel regionGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 8, 2017·5 cites·9 claims
- 3288US9875939B1Methods of forming uniform and pitch independent fin recessGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 23, 2018·5 cites·20 claims
- 3388US6180486B1Process of fabricating planar and densely patterned silicon-on-insulator structureIBM·Filed 1999·Granted Jan 30, 2001·80 cites·8 claims
- 3487US9722052B2Fin cut without residual fin defectsIBM·Filed 2015·Granted Aug 1, 2017·4 cites·14 claims
- 3587US9472460B1Uniform depth fin trench formationGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 18, 2016·4 cites·20 claims
- 3687US9123826B1Single crystal source-drain merged by polycrystalline materialIBM·Filed 2014·Granted Sep 1, 2015·8 cites·20 claims
- 3787US6884667B1Field effect transistor with stressed channel and method for making sameIBM·Filed 2003·Granted Apr 26, 2005·36 cites·4 claims
- 3886US8685806B2Silicon-on-insulator substrate with built-in substrate junctionIBM·Filed 2013·Granted Apr 1, 2014·6 cites·20 claims
- 3986US8643061B2Structure of high-K metal gate semiconductor transistorYIN HAIZHOU·Filed 2010·Granted Feb 4, 2014·8 cites·20 claims
- 4086US6440807B1Surface engineering to prevent EPI growth on gate poly during selective EPI processingIBM·Filed 2001·Granted Aug 27, 2002·31 cites·20 claims
- 4186US5646053AMethod and structure for front-side gettering of silicon-on-insulator substratesIBM·Filed 1995·Granted Jul 8, 1997·82 cites·43 claims
- 4286US5298784AElectrically programmable antifuse using metal penetration of a junctionIBM·Filed 1992·Granted Mar 29, 1994·87 cites·20 claims
- 4384US7446350B2Embedded silicon germanium using a double buried oxide silicon-on-insulator waferIBM·Filed 2005·Granted Nov 4, 2008·9 cites·18 claims
- 4484US6429488B2Densely patterned silicon-on-insulator (SOI) region on a waferIBM·Filed 2001·Granted Aug 6, 2002·33 cites·14 claims
- 4583US10170304B1Self-aligned nanotube structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 1, 2019·3 cites·20 claims
- 4683US8232186B2Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structureHARLEY ERIC C T·Filed 2008·Granted Jul 31, 2012·13 cites·16 claims
- 4783US8173524B1Process for epitaxially growing epitaxial material regionsCHAKRAVARTI ASHIMA B·Filed 2011·Granted May 8, 2012·6 cites·24 claims
- 4883US7955940B2Silicon-on-insulator substrate with built-in substrate junctionIBM·Filed 2009·Granted Jun 7, 2011·8 cites·13 claims
- 4983US6835633B2SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layerIBM·Filed 2002·Granted Dec 28, 2004·24 cites·7 claims
- 5083US6506649B2Method for forming notch gate having self-aligned raised source/drain structureIBM·Filed 2001·Granted Jan 14, 2003·33 cites·13 claims
Showing the top 50 of 160 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →