Inventor · disambiguated record
Jyh-Rong Lin
Also filed as: LIN JYH-RONG
18 granted patents·4 pending applications·535 citations·filing 1999–2019
95Inventor score
Files withIND TECH RES INST9HUAWEI TECH CO LTD5CHEN SHOU-LUNG2INVENSAS CORP2HK APPLIED SCIENCE & TECH RES1
Top patents by PatentIndex Score
22 records- 0197US7294920B2Wafer-leveled chip packaging structure and method thereofIND TECH RES INST·Filed 2005·Granted Nov 13, 2007·92 cites·5 claims
- 0295US6277669B1Wafer level packaging method and packages formedIND TECH RES INST·Filed 1999·Granted Aug 21, 2001·274 cites·22 claims
- 0392US7528009B2Wafer-leveled chip packaging structure and method thereofIND TECH RES INST·Filed 2007·Granted May 5, 2009·20 cites·18 claims
- 0487US8248803B2Semiconductor package and method of manufacturing the sameLIN JYH-RONG·Filed 2010·Granted Aug 21, 2012·17 cites·9 claims
- 0587US7411306B2Packaging structure and method of an image sensor moduleIND TECH RES INST·Filed 2005·Granted Aug 12, 2008·17 cites·11 claims
- 0682US10490506B2Packaged chip and signal transmission method based on packaged chipHUAWEI TECH CO LTD·Filed 2017·Granted Nov 26, 2019·5 cites·18 claims
- 0782US6358836B1Wafer level package incorporating elastomeric pads in dummy plugsIND TECH RES INST·Filed 2000·Granted Mar 19, 2002·42 cites·15 claims
- 0881US7572676B2Packaging structure and method of an image sensor moduleIND TECH RES INST·Filed 2007·Granted Aug 11, 2009·10 cites·12 claims
- 0980US8314482B2Semiconductor package deviceCHEN SHOU-LUNG·Filed 2007·Granted Nov 20, 2012·8 cites·20 claims
- 1080US6605525B2Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formedIND TECHNOLOGIES RES INST·Filed 2001·Granted Aug 12, 2003·34 cites·12 claims
- 1179US10784181B2Apparatus and manufacturing methodHUAWEI TECH CO LTD·Filed 2018·Granted Sep 22, 2020·4 cites·19 claims
- 1276US7879438B2Substrate warpage-reducing structureHK APPLIED SCIENCE & TECH RES·Filed 2009·Granted Feb 1, 2011·5 cites·8 claims
- 1371US9059181B2Wafer leveled chip packaging structure and method thereofINVENSAS CORP·Filed 2013·Granted Jun 16, 2015·2 cites·14 claims
- 1467US10475741B2ChipHUAWEI TECH CO LTD·Filed 2017·Granted Nov 12, 2019·1 cites·13 claims
- 1567US7632707B2Electronic device package and method of manufacturing the sameIND TECH RES INST·Filed 2005·Granted Dec 15, 2009·3 cites·8 claims
- 1664US8587091B2Wafer-leveled chip packaging structure and method thereofCHEN SHOU-LUNG·Filed 2012·Granted Nov 19, 2013·1 cites·4 claims
- 1754US7838333B2Electronic device package and method of manufacturing the sameIND TECH RES INST·Filed 2009·Granted Nov 23, 2010·0 cites·18 claims
- 1842US2020135615A1Chip package structureHUAWEI TECH CO LTD·Filed 2019·Application pending·0 cites
- 1942US2009115051A1Electronic Circuit PackageLEUNG LAP-WAI LYDIA·Filed 2007·Application pending·0 cites
- 2036US9601474B2Electrically stackable semiconductor wafer and chip packagesINVENSAS CORP·Filed 2015·Granted Mar 21, 2017·0 cites·16 claims
- 2136US2019198422A1Semiconductor apparatus and manufacturing method thereofHUAWEI TECH CO LTD·Filed 2019·Application pending·0 cites
- 2232US2003107132A1Structure of the metal bumping on the input/output connector of a substrate or wafer and method for manufacturing the sameIND TECH RES INST·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →