Inventor · disambiguated record
Balasubramanian S. Pranatharthi Haran
Also filed as: PRANATHARTHI HARAN BALASUBRAMANIAN · PRANATHARTHI HARAN BALASUBRAMANIAN S
23 granted patents·1 pending application·138 citations·filing 2004–2021
95Inventor score
Files withIBM17GLOBALFOUNDRIES INC3CABRAL JR CYRIL1FULLER NICHOLAS C1GLOBALFOUNFRIES SINGAPORE PTE LTD1
Top patents by PatentIndex Score
24 records- 0197US9741609B1Middle of line cobalt interconnectionIBM·Filed 2016·Granted Aug 22, 2017·22 cites·14 claims
- 0297US8772168B2Formation of the dielectric cap layer for a replacement gate structureXIE RUILONG·Filed 2012·Granted Jul 8, 2014·34 cites·7 claims
- 0391US11171054B2Selective deposition with SAM for fully aligned viaIBM·Filed 2020·Granted Nov 9, 2021·3 cites·16 claims
- 0491US10600638B2Nanosheet transistors with sharp junctionsIBM·Filed 2016·Granted Mar 24, 2020·6 cites·12 claims
- 0589US10497612B2Methods of forming contact structures on integrated circuit productsGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 3, 2019·4 cites·20 claims
- 0689US9455254B2Methods of forming a combined gate and source/drain contact structure and the resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 27, 2016·10 cites·23 claims
- 0788US11133217B1Late gate cut with optimized contact trench sizeIBM·Filed 2020·Granted Sep 28, 2021·2 cites·19 claims
- 0887US11164782B2Self-aligned gate contact compatible cross couple contact formationIBM·Filed 2020·Granted Nov 2, 2021·2 cites·19 claims
- 0986US8101518B2Method and process for forming a self-aligned silicide contactCABRAL JR CYRIL·Filed 2008·Granted Jan 24, 2012·12 cites·27 claims
- 1084US8957465B2Formation of the dielectric cap layer for a replacement gate structureGLOBALFOUNFRIES SINGAPORE PTE LTD·Filed 2014·Granted Feb 17, 2015·8 cites·17 claims
- 1180US11189528B2Subtractive RIE interconnectIBM·Filed 2020·Granted Nov 30, 2021·1 cites·20 claims
- 1280US11152464B1Self-aligned isolation for nanosheet transistorIBM·Filed 2020·Granted Oct 19, 2021·1 cites·14 claims
- 1380US8698318B2Superfilled metal contact vias for semiconductor devicesIBM·Filed 2013·Granted Apr 15, 2014·4 cites·19 claims
- 1479US9704991B1Gate height and spacer uniformityIBM·Filed 2016·Granted Jul 11, 2017·2 cites·14 claims
- 1576US7501345B1Selective silicide formation by electrodeposit displacement reactionIBM·Filed 2008·Granted Mar 10, 2009·5 cites·4 claims
- 1674US7914970B2Mixed lithography with dual resist and a single pattern transferIBM·Filed 2007·Granted Mar 29, 2011·6 cites·16 claims
- 1770US7544610B2Method and process for forming a self-aligned silicide contactIBM·Filed 2004·Granted Jun 9, 2009·14 cites·34 claims
- 1863US10872809B2Contact structures for integrated circuit productsGLOBALFOUNDRIES INC·Filed 2019·Granted Dec 22, 2020·0 cites·20 claims
- 1958US8334090B2Mixed lithography with dual resist and a single pattern transferFULLER NICHOLAS C·Filed 2011·Granted Dec 18, 2012·2 cites·10 claims
- 2056US10586741B2Gate height and spacer uniformityIBM·Filed 2017·Granted Mar 10, 2020·0 cites·20 claims
- 2154US11430651B2Nanosheet transistors with sharp junctionsIBM·Filed 2018·Granted Aug 30, 2022·0 cites·6 claims
- 2254US11355633B2Vertical field effect transistor with bottom source-drain regionIBM·Filed 2020·Granted Jun 7, 2022·0 cites·6 claims
- 2351US2023154784A1Bottom dielectric isolation integration with buried power railIBM·Filed 2021·Application pending·0 cites
- 2450US11302637B2Interconnects including dual-metal viasIBM·Filed 2020·Granted Apr 12, 2022·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →