Inventor · disambiguated record
Mark D. Jacunski
Also filed as: JACUNSKI MARK · JACUNSKI MARK D · JACUNSKI MARK DAVID
21 granted patents·1 pending application·317 citations·filing 2000–2021
95Inventor score
Top patents by PatentIndex Score
22 records- 0196US6399990B1Isolated well ESD deviceIBM·Filed 2000·Granted Jun 4, 2002·132 cites·19 claims
- 0295US10429434B2On-chip reliability monitor and methodGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 1, 2019·6 cites·20 claims
- 0394US9093175B2Signal margin centering for single-ended eDRAM sense amplifierIBM·Filed 2013·Granted Jul 28, 2015·19 cites·20 claims
- 0492US9870979B2Double-sided segmented line architecture in 3D integrationIBM·Filed 2015·Granted Jan 16, 2018·10 cites·7 claims
- 0592US9559040B2Double-sided segmented line architecture in 3D integrationIBM·Filed 2013·Granted Jan 31, 2017·14 cites·10 claims
- 0689US6400202B1Programmable delay element and synchronous DRAM using the sameIBM·Filed 2001·Granted Jun 4, 2002·48 cites·7 claims
- 0778US6348827B1Programmable delay element and synchronous DRAM using the sameIBM·Filed 2000·Granted Feb 19, 2002·24 cites·6 claims
- 0875US9779783B2Latching current sensing amplifier for memory arrayIBM·Filed 2015·Granted Oct 3, 2017·3 cites·15 claims
- 0973USRE50596EOn-chip reliability monitor and methodMARVELL ASIA PTE LTD·Filed 2021·Granted Sep 23, 2025·0 cites·38 claims
- 1071US8902679B2Memory array with on and off-state wordline voltages having different temperature coefficientsFIFIELD JOHN A·Filed 2012·Granted Dec 2, 2014·4 cites·20 claims
- 1167US10020047B2Static random access memory (SRAM) write assist circuit with improved boostGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 10, 2018·2 cites·9 claims
- 1265US6693843B1Wordline on and off voltage compensation circuit based on the array device threshold voltageINFINEON TECHNOLOGIES AG·Filed 2002·Granted Feb 17, 2004·14 cites·12 claims
- 1364US7221601B2Timer lockout circuit for synchronous applicationsIBM·Filed 2006·Granted May 22, 2007·5 cites·18 claims
- 1460US6580655B2Pre-charge circuit and method for memory devices with shared sense amplifiersIBM·Filed 2001·Granted Jun 17, 2003·12 cites·13 claims
- 1558US6580650B2DRAM word line voltage control to insure full cell writeback levelIBM·Filed 2001·Granted Jun 17, 2003·10 cites·28 claims
- 1656US7194670B2Command multiplier for built-in-self-testIBM·Filed 2004·Granted Mar 20, 2007·9 cites·8 claims
- 1748US10535379B2Latching current sensing amplifier for memory arrayGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 14, 2020·0 cites·19 claims
- 1845US6522154B2Oxide tracking voltage referenceIBM·Filed 2001·Granted Feb 18, 2003·3 cites·14 claims
- 1939US7068564B2Timer lockout circuit for synchronous applicationsIBM·Filed 2003·Granted Jun 27, 2006·2 cites·20 claims
- 2035US8649239B2Multi-bank random access memory structure with global and local signal buffering for improved performanceANAND DARREN L·Filed 2012·Granted Feb 11, 2014·0 cites·25 claims
- 2133US7085180B2Method and structure for enabling a redundancy allocation during a multi-bank operationIBM·Filed 2004·Granted Aug 1, 2006·0 cites·19 claims
- 2233US2012036315A1Morphing Memory ArchitectureREOHR WILLIAM R·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →