Inventor · disambiguated record
John K. Debrosse
Also filed as: DEBROSSE JOHN · DEBROSSE JOHN K · DEBROSSE JOHN KENNETH
93 granted patents·1 pending application·2,349 citations·filing 1988–2021
99Inventor score
Top patents by PatentIndex Score
94 records- 0199US7376006B2Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage elementIBM·Filed 2005·Granted May 20, 2008·138 cites·12 claims
- 0298US5606188AFabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memoryIBM·Filed 1995·Granted Feb 25, 1997·253 cites·13 claims
- 0397US6982902B2MRAM array having a segmented bit lineIBM·Filed 2003·Granted Jan 3, 2006·149 cites·43 claims
- 0496US9373783B1Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxyIBM·Filed 2015·Granted Jun 21, 2016·13 cites·11 claims
- 0596US7514271B2Method of forming high density planar magnetic domain wall memoryIBM·Filed 2007·Granted Apr 7, 2009·36 cites·10 claims
- 0696US6704230B1Error detection and correction method and apparatus in a magnetoresistive random access memoryIBM·Filed 2003·Granted Mar 9, 2004·126 cites·20 claims
- 0795US10726897B1Trimming MRAM sense amp with offset cancellationIBM·Filed 2019·Granted Jul 28, 2020·17 cites·20 claims
- 0895US6490217B1Select line architecture for magnetic random access memoriesIBM·Filed 2001·Granted Dec 3, 2002·108 cites·28 claims
- 0995US6282113B1Four F-squared gapless dual layer bitline DRAM array architectureIBM·Filed 1999·Granted Aug 28, 2001·127 cites·22 claims
- 1095US5360758ASelf-aligned buried strap for trench type DRAM cellsIBM·Filed 1993·Granted Nov 1, 1994·109 cites·7 claims
- 1193US10115450B1Cascode complimentary dual level shifterIBM·Filed 2017·Granted Oct 30, 2018·10 cites·17 claims
- 1293US9875780B1STT MRAM source line configurationIBM·Filed 2016·Granted Jan 23, 2018·14 cites·16 claims
- 1393US9496018B2Nonvolatile memory interface for metadata shadowingIBM·Filed 2015·Granted Nov 15, 2016·8 cites·11 claims
- 1493US7535783B2Apparatus and method for implementing precise sensing of PCRAM devicesIBM·Filed 2007·Granted May 19, 2009·32 cites·21 claims
- 1592US7239537B2Method and apparatus for current sense amplifier calibration in MRAM devicesIBM·Filed 2005·Granted Jul 3, 2007·29 cites·12 claims
- 1692US5508219ASOI DRAM with field-shield isolation and body contactIBM·Filed 1995·Granted Apr 16, 1996·108 cites·16 claims
- 1791US6946882B2Current sense amplifierIBM·Filed 2002·Granted Sep 20, 2005·61 cites·36 claims
- 1891US6816403B1Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devicesIBM·Filed 2003·Granted Nov 9, 2004·61 cites·14 claims
- 1991US4873205AMethod for providing silicide bridge contact between silicon regions separated by a thin dielectricIBM·Filed 1988·Granted Oct 10, 1989·111 cites·17 claims
- 2090US9343131B1Mismatch and noise insensitive sense amplifier circuit for STT MRAMIBM·Filed 2015·Granted May 17, 2016·9 cites·12 claims
- 2189US9786343B1STT MRAM common source line array bias schemeIBM·Filed 2016·Granted Oct 10, 2017·9 cites·20 claims
- 2289US9384792B2Offset-cancelling self-reference STT-MRAM sense amplifierGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 5, 2016·12 cites·10 claims
- 2389US8835256B1Memory array with self-aligned epitaxially grown memory elements and annular FETIBM·Filed 2013·Granted Sep 16, 2014·9 cites·7 claims
- 2489US8023305B2High density planar magnetic domain wall memory apparatusIBM·Filed 2008·Granted Sep 20, 2011·11 cites·10 claims
- 2589US8009453B2High density planar magnetic domain wall memory apparatusIBM·Filed 2008·Granted Aug 30, 2011·15 cites·10 claims
- 2689US6255683B1Dynamic random access memoryINFINEON TECHNOLOGIES AG·Filed 1998·Granted Jul 3, 2001·66 cites·2 claims
- 2787US10741232B1Tunable reference system with sense amplifier offset cancellation for magnetic random access memoryIBM·Filed 2019·Granted Aug 11, 2020·9 cites·12 claims
- 2886US8446757B2Spin-torque transfer magneto-resistive memory architectureDEBROSSE JOHN K·Filed 2010·Granted May 21, 2013·8 cites·8 claims
- 2986US6351019B1Planarized and fill biased integrated circuit chipIBM·Filed 2000·Granted Feb 26, 2002·36 cites·4 claims
- 3085US9373383B2STT-MRAM sensing techniqueIBM·Filed 2014·Granted Jun 21, 2016·8 cites·20 claims
- 3184US8828743B1Structure and fabrication of memory array with epitaxially grown memory elements and line-space patternsIBM·Filed 2013·Granted Sep 9, 2014·5 cites·6 claims
- 3282US9450179B2Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxyIBM·Filed 2015·Granted Sep 20, 2016·3 cites·8 claims
- 3382US6944049B2Magnetic tunnel junction memory cell architectureIBM·Filed 2003·Granted Sep 13, 2005·31 cites·23 claims
- 3482US5534732ASingle twist layout and method for paired line conductors of integrated circuitsIBM·Filed 1995·Granted Jul 9, 1996·73 cites·15 claims
- 3582US5525531ASOI DRAM with field-shield isolationIBM·Filed 1995·Granted Jun 11, 1996·54 cites·16 claims
- 3681US9613674B2Mismatch and noise insensitive sense amplifier circuit for STT MRAMIBM·Filed 2016·Granted Apr 4, 2017·4 cites·20 claims
- 3781US8917531B2Cell design for embedded thermally-assisted MRAMIBM·Filed 2013·Granted Dec 23, 2014·3 cites·18 claims
- 3880US9378795B1Mismatch and noise insensitive sense amplifier circuit for STT MRAMIBM·Filed 2015·Granted Jun 28, 2016·4 cites·9 claims
- 3980US7596045B2Design structure for initializing reference cells of a toggle switched MRAM deviceIBM·Filed 2007·Granted Sep 29, 2009·12 cites·8 claims
- 4080US5614431AMethod of making buried strap trench cell yielding an extended transistorIBM·Filed 1995·Granted Mar 25, 1997·52 cites·4 claims
- 4180US5546349AExchangeable hierarchical data line structureTOSHIBA KK·Filed 1995·Granted Aug 13, 1996·46 cites·7 claims
- 4279US8331125B2Array architecture and operation for high density magnetic racetrack memory systemDEBROSSE JOHN K·Filed 2009·Granted Dec 11, 2012·11 cites·20 claims
- 4378US5963489AMethod and apparatus for redundancy word line replacement in a repairable semiconductor memory deviceIBM·Filed 1998·Granted Oct 5, 1999·43 cites·21 claims
- 4477US9536926B1Magnetic tunnel junction based anti-fuses with cascoded transistorsIBM·Filed 2015·Granted Jan 3, 2017·2 cites·13 claims
- 4577US9471422B2Adaptive error correction in a memory systemIBM·Filed 2015·Granted Oct 18, 2016·3 cites·7 claims
- 4677US5691946ARow redundancy block architectureIBM·Filed 1996·Granted Nov 25, 1997·41 cites·17 claims
- 4776US10374152B2Magnetic tunnel junction based anti-fuses with cascoded transistorsIBM·Filed 2016·Granted Aug 6, 2019·2 cites·17 claims
- 4876US9852784B2Bit line clamp voltage generator for STT MRAM sensingIBM·Filed 2017·Granted Dec 26, 2017·3 cites·12 claims
- 4976US5821592ADynamic random access memory arrays and methods thereforSIEMENS AG·Filed 1997·Granted Oct 13, 1998·33 cites·20 claims
- 5076US5602051AMethod of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack levelIBM·Filed 1995·Granted Feb 11, 1997·30 cites·7 claims
Showing the top 50 of 94 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →