Inventor · disambiguated record
Mahbub Rashed
Also filed as: RASHED MAHBUB · RASHED MAHBUB M
74 granted patents·11 pending applications·482 citations·filing 2005–2025
99Inventor score
Files withGLOBALFOUNDRIES INC41GLOBALFOUNDRIES US INC23RASHED MAHBUB7FREESCALE SEMICONDUCTOR INC6YUAN LEI2
Top patents by PatentIndex Score
85 records- 0198US9337099B1Special constructs for continuous non-uniform active region FinFET standard cellsGLOBALFOUNDRIES INC·Filed 2015·Granted May 10, 2016·53 cites·12 claims
- 0295US7138842B2Flip-flop circuit having low power data retentionFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Nov 21, 2006·37 cites·20 claims
- 0394US12046603B2Semiconductor structure including sectioned well regionGLOBALFOUNDRIES US INC·Filed 2021·Granted Jul 23, 2024·2 cites·20 claims
- 0494US10199378B2Special construct for continuous non-uniform active region FinFET standard cellsGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 5, 2019·8 cites·20 claims
- 0594US8881083B1Methods for improving double patterning route efficiencyGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 4, 2014·19 cites·20 claims
- 0694US8741763B2Layout designs with via routing structuresMA YUANSHENG·Filed 2012·Granted Jun 3, 2014·38 cites·17 claims
- 0793US11322200B1Single-rail memory circuit with row-specific voltage supply lines and boost circuitsGLOBALFOUNDRIES US INC·Filed 2020·Granted May 3, 2022·4 cites·20 claims
- 0893US8581348B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted Nov 12, 2013·20 cites·16 claims
- 0992US11444031B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2020·Granted Sep 13, 2022·2 cites·13 claims
- 1092US10366954B1Structure and method for flexible power staple insertionGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 30, 2019·8 cites·6 claims
- 1192US9122830B2Wide pin for improved circuit routingGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 1, 2015·12 cites·20 claims
- 1292US8679911B2Cross-coupling-based design using diffusion contact structuresWANG YAN·Filed 2012·Granted Mar 25, 2014·14 cites·12 claims
- 1391US9893063B2Special construct for continuous non-uniform active region FinFET standard cellsGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 13, 2018·6 cites·11 claims
- 1491US9355910B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted May 31, 2016·10 cites·7 claims
- 1591US9035679B2Standard cell connection for circuit routingGLOBALFOUNDRIES INC·Filed 2013·Granted May 19, 2015·13 cites·15 claims
- 1691US8987128B2Cross-coupling based design using diffusion contact structuresRASHED MAHBUB·Filed 2012·Granted Mar 24, 2015·22 cites·20 claims
- 1791US8975712B2Densely packed standard cells for integrated circuit products, and methods of making sameGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 10, 2015·14 cites·15 claims
- 1891US8618607B1Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making sameRASHED MAHBUB·Filed 2012·Granted Dec 31, 2013·17 cites·36 claims
- 1991US7274247B2System, method and program product for well-bias set point adjustmentFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Sep 25, 2007·28 cites·19 claims
- 2090US9026977B2Power rail layout for dense standard cell libraryGLOBALFOUNDRIES INC·Filed 2013·Granted May 5, 2015·15 cites·6 claims
- 2189US9196548B2Methods of using a trench salicide routing layerRASHED MAHBUB·Filed 2012·Granted Nov 24, 2015·11 cites·18 claims
- 2288US10819110B2Electrostatic discharge protection deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·5 cites·20 claims
- 2388US2025038111A1Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 2487US10360334B2Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell libraryGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 23, 2019·5 cites·20 claims
- 2587US9159724B2Cross-coupling-based design using diffusion contact structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 13, 2015·8 cites·20 claims
- 2687US9006100B2Middle-of-the-line constructs using diffusion contact structuresRASHED MAHBUB·Filed 2012·Granted Apr 14, 2015·9 cites·14 claims
- 2786US10242946B2Circuit design having aligned power staplesGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 26, 2019·5 cites·20 claims
- 2885US10833018B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 10, 2020·2 cites·20 claims
- 2982US10347543B2FDSOI semiconductor device with contact enhancement layer and method of manufacturingGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 9, 2019·4 cites·19 claims
- 3081US9530780B2Memory bit cell for reduced layout areaGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 27, 2016·3 cites·10 claims
- 3180US9519745B2Method and apparatus for assisted metal routingGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 13, 2016·5 cites·10 claims
- 3280US8735050B2Integrated circuits and methods for fabricating integrated circuits using double patterning processesYUAN LEI·Filed 2012·Granted May 27, 2014·3 cites·18 claims
- 3379US12148702B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2022·Granted Nov 19, 2024·0 cites·20 claims
- 3479US9634003B2Special construct for continuous non-uniform RX FinFET standard cellsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 25, 2017·2 cites·11 claims
- 3579US8966423B2Integrating optimal planar and three-dimensional semiconductor design layoutsGLOBALFOUNDARIES INC·Filed 2013·Granted Feb 24, 2015·5 cites·12 claims
- 3679US8677291B1Double patterning compatible colorless M1 routeYUAN LEI·Filed 2012·Granted Mar 18, 2014·6 cites·19 claims
- 3778US9292647B2Method and apparatus for modified cell architecture and the resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 22, 2016·4 cites·18 claims
- 3878US9147028B2Forming modified cell architecture for finFET technology and resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 29, 2015·4 cites·17 claims
- 3978US9142513B2Middle-of-the-line constructs using diffusion contact structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 22, 2015·3 cites·20 claims
- 4077US9536035B2Wide pin for improved circuit routingGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 3, 2017·2 cites·20 claims
- 4177US8859416B2Software and method for via spacing in a semiconductor deviceDOMAN DAVID S·Filed 2012·Granted Oct 14, 2014·8 cites·20 claims
- 4276US9105643B2Bit cell with double patterned metal layer structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 11, 2015·3 cites·12 claims
- 4375US10108771B2Method, apparatus and system for forming recolorable standard cells with triple patterned metal layer structuresGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 23, 2018·2 cites·21 claims
- 4475US9391080B1Memory bit cell for reduced layout areaGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 12, 2016·2 cites·12 claims
- 4575US8823178B2Bit cell with double patterned metal layer structuresKIM JUHAN·Filed 2012·Granted Sep 2, 2014·3 cites·5 claims
- 4674US10658294B2Structure and method for flexible power staple insertionGLOBALFOUNDRIES INC·Filed 2019·Granted May 19, 2020·1 cites·20 claims
- 4774US8789000B1Variable power rail designGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 22, 2014·3 cites·20 claims
- 4874US7741195B2Method of stimulating die circuitry and structure thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jun 22, 2010·5 cites·20 claims
- 4974US7542360B2Programmable bias for a memory arrayFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 2, 2009·10 cites·20 claims
- 5072US12183394B2Circuit structure and related method for radiation resistant memory cellGLOBALFOUNDRIES US INC·Filed 2023·Granted Dec 31, 2024·0 cites·20 claims
Showing the top 50 of 85 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →