Inventor · disambiguated record
Seyhan Karakulak
Also filed as: KARAKULAK SEYHAN
15 granted patents·5 pending applications·131 citations·filing 2012–2024
91Inventor score
Top patents by PatentIndex Score
20 records- 0197US9720754B2Read level grouping for increased flash performanceHGST Netherlands BV·Filed 2015·Granted Aug 1, 2017·40 cites·20 claims
- 0296US9576671B2Calibrating optimal read levelsHGST Netherlands BV·Filed 2014·Granted Feb 21, 2017·29 cites·20 claims
- 0395US8493791B2Word-line inter-cell interference detector in flash systemSTEC INC·Filed 2012·Granted Jul 23, 2013·26 cites·23 claims
- 0493US10566061B2Calibrating optimal read levelsWESTERN DIGITAL TECH INC·Filed 2017·Granted Feb 18, 2020·12 cites·20 claims
- 0591US11574698B1Compressing deep neural networks used in memory devicesSK HYNIX INC·Filed 2021·Granted Feb 7, 2023·2 cites·20 claims
- 0691US9905302B2Read level grouping algorithms for increased flash performanceWESTERN DIGITAL TECH INC·Filed 2014·Granted Feb 27, 2018·14 cites·24 claims
- 0782US9117529B2Inter-cell interference algorithms for soft decoding of LDPC codesSTEC INC·Filed 2012·Granted Aug 25, 2015·7 cites·30 claims
- 0874US11815996B2Method and system for identifying erased memory areasWESTERN DIGITAL TECH INC·Filed 2022·Granted Nov 14, 2023·0 cites·20 claims
- 0967US11327837B2Method and system for identifying erased memory areasWESTERN DIGITAL TECH INC·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 1067US10387246B2Method and system for scanning for erased flash memory pagesWESTERN DIGITAL TECH INC·Filed 2017·Granted Aug 20, 2019·1 cites·21 claims
- 1165US2025181134A1Managing power state transitions using machine learning in a memory sub-systemMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1263US11488673B2Calibrating optimal read levelsWESTERN DIGITAL TECH INC·Filed 2020·Granted Nov 1, 2022·0 cites·20 claims
- 1358US2025117137A1Self-optimization of data placement in memory or storage systemsMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1457US11621727B2Decoding systems and methods for local reinforcementSK HYNIX INC·Filed 2021·Granted Apr 4, 2023·0 cites·16 claims
- 1554US10884854B2Method and system for identifying erased memory areasWESTERN DIGITAL TECH INC·Filed 2019·Granted Jan 5, 2021·0 cites·20 claims
- 1652US11881869B1Asymmetric bit errors in low-density parity-check codes for non-volatile memory devicesSK HYNIX INC·Filed 2022·Granted Jan 23, 2024·0 cites·20 claims
- 1750US2024086149A1Constrained clustering algorithm for efficient hardware implementation of a deep neural network engineSK HYNIX INC·Filed 2022·Application pending·0 cites
- 1846US2024112020A1Non-uniform quantization for flexible power-of-two computations in neural networksSK HYNIX INC·Filed 2022·Application pending·0 cites
- 1943US9343170B2Word-line inter-cell interference detector in flash systemHGST Netherlands BV·Filed 2014·Granted May 17, 2016·0 cites·20 claims
- 2039US2015364202A1Inter-cell interference algorithms for soft decoding of ldpc codesHGST TECHNOLOGIES SANTA ANA INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →