Inventor · disambiguated record
Youn Sung Choi
Also filed as: CHOI YOUN SUNG
24 granted patents·7 pending applications·104 citations·filing 2010–2021
94Inventor score
Top patents by PatentIndex Score
31 records- 0195US9029263B1Method of printing multiple structure widths using spacer double patterningTEXAS INSTRUMENTS INC·Filed 2014·Granted May 12, 2015·25 cites·20 claims
- 0294US9634138B1Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layoutQUALCOMM INC·Filed 2016·Granted Apr 25, 2017·15 cites·19 claims
- 0394US9093298B2Silicide formation due to improved SiGe facetingTEXAS INSTRUMENTS INC·Filed 2013·Granted Jul 28, 2015·14 cites·12 claims
- 0489US8859357B2Method for improving device performance using dual stress liner boundaryCHOI YOUN SUNG·Filed 2011·Granted Oct 14, 2014·10 cites·9 claims
- 0584US10490558B2Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cellsQUALCOMM INC·Filed 2017·Granted Nov 26, 2019·4 cites·14 claims
- 0684US9882051B1Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regionsQUALCOMM INC·Filed 2016·Granted Jan 30, 2018·4 cites·23 claims
- 0783US8987748B2Drain induced barrier lowering with anti-punch-through implantTEXAS INSTRUMENTS INC·Filed 2012·Granted Mar 24, 2015·6 cites·20 claims
- 0882US10950488B2Integration of finFET deviceTEXAS INSTRUMENTS INC·Filed 2019·Granted Mar 16, 2021·2 cites·15 claims
- 0982US9543437B2Integrated circuit with dual stress liner boundaryTEXAS INSTRUMENTS INC·Filed 2015·Granted Jan 10, 2017·2 cites·7 claims
- 1081US10062768B2Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layoutQUALCOMM INC·Filed 2017·Granted Aug 28, 2018·3 cites·16 claims
- 1178US9412741B2Integration of analog transistorTEXAS INSTRUMENTS INC·Filed 2015·Granted Aug 9, 2016·2 cites·6 claims
- 1278US8748256B2Integrated circuit having silicide block resistorZHAO SONG·Filed 2012·Granted Jun 10, 2014·7 cites·11 claims
- 1375US9171901B2Method for improving device performance using dual stress liner boundaryTEXAS INSTRUMENTS INC·Filed 2014·Granted Oct 27, 2015·2 cites·6 claims
- 1473US9202810B2Integration of analog transistorTEXAS INSTRUMENTS INC·Filed 2014·Granted Dec 1, 2015·2 cites·14 claims
- 1569US8669775B2Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devicesCHOI YOUN SUNG·Filed 2010·Granted Mar 11, 2014·3 cites·16 claims
- 1667US9202883B2Silicide formation due to improved SiGe facetingTEXAS INSTRUMENTS INC·Filed 2015·Granted Dec 1, 2015·1 cites·8 claims
- 1766US8664968B2On-die parametric test modules for in-line monitoring of context dependent effectsBALDWIN GREGORY CHARLES·Filed 2010·Granted Mar 4, 2014·2 cites·16 claims
- 1861US10996261B2Sensor for gate leakage detectionQUALCOMM INC·Filed 2018·Granted May 4, 2021·0 cites·9 claims
- 1959US11444201B2Leakage current reduction in polysilicon-on-active-edge structuresQUALCOMM INC·Filed 2020·Granted Sep 13, 2022·0 cites·18 claims
- 2059US9953967B2Integrated circuit with dual stress liner boundaryTEXAS INSTRUMENTS INC·Filed 2016·Granted Apr 24, 2018·0 cites·7 claims
- 2155US9406769B2Silicide formation due to improved SiGe facetingTEXAS INSTRUMENTS INC·Filed 2015·Granted Aug 2, 2016·0 cites·8 claims
- 2255US2015171217A1Design and integration of finfet deviceTEXAS INSTRUMENTS INC·Filed 2014·Application pending·0 cites
- 2354US9922971B2Integration of analog transistorTEXAS INSTRUMENTS INC·Filed 2016·Granted Mar 20, 2018·0 cites·20 claims
- 2454US2018108564A1Design and integration of finfet deviceTEXAS INSTRUMENTS INC·Filed 2017·Application pending·0 cites
- 2550US10600774B2Systems and methods for fabrication of gated diodes with selective epitaxial growthQUALCOMM INC·Filed 2018·Granted Mar 24, 2020·0 cites·21 claims
- 2649US11075206B2SRAM source-drain structureQUALCOMM INC·Filed 2018·Granted Jul 27, 2021·0 cites·17 claims
- 2746US2022216328A1Gate-to-contact short prevention with an inner spacerQUALCOMM INC·Filed 2021·Application pending·0 cites
- 2842US2021143153A1Fin field-effect transistor (fet) (finfet) circuits employing replacement n-type fet (nfet) source/drain (s/d) to avoid or prevent short defects and related methods of fabricationQUALCOMM INC·Filed 2019·Application pending·0 cites
- 2939US2013249011A1Integrated circuit (ic) having tsvs and stress compensating layerCHOI YOUN SUNG·Filed 2012·Application pending·0 cites
- 3037US2020256915A1Inline monitoring test structureQUALCOMM INC·Filed 2019·Application pending·0 cites
- 3137US2014054710A1Reduction of Proximity Effects in Field-Effect Transistors with Embedded Silicon-Germanium Source and Drain RegionsCHOI YOUN SUNG·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →