Design and integration of finfet device

Abstract

An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.

What is claimed is: 
     
         1 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate comprising a semiconductor material;   forming a first fin of semiconductor material of a first finFET and a second fin of semiconductor material of a second finFET on the substrate, so that a fin height of the first fin is substantially equal to a fin height of the second fin;   forming isolation oxide over the substrate adjacent to the first fin and the second fin, so that the first fin and the second fin extend above the isolation oxide;   forming an etch mask over the first fin, the second fin and the isolation oxide which exposes the first fin and covers the second fin;   removing the semiconductor material from a top of the first fin without removing the semiconductor material from a top of the second fin, so that an exposed fin height of the first fin is at least 25 percent less than an exposed fin height of the second fin; and   forming a first gate of the first finFET over the first fin so as to extend down sidewalls of the first fin substantially to the isolation oxide and forming a second gate of the second finFET over the second fin so as to extend down sidewalls of the second fin substantially to the isolation oxide.   
     
     
         2 . The method of  claim 1 , wherein:
 the first finFET is a passgate finFET in an SRAM cell; and   the second finFET is a driver finFET in the SRAM cell.   
     
     
         3 . The method of  claim 1 , wherein the first fin and the second fin are formed with substantially equal widths. 
     
     
         4 . The method of  claim 1 , wherein the first fin and fins adjacent to the first fin, and the second fin and fins adjacent to the second fin, are formed on substantially equal pitch distances. 
     
     
         5 . The method of  claim 1 , wherein the first gate and the second gate are formed with substantially equal widths. 
     
     
         6 . The method of  claim 1 , wherein the first gate and gates adjacent to the first gate, and the second gate and gates adjacent to the second gate, are formed on substantially equal pitch distances. 
     
     
         7 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate comprising a semiconductor material;   forming a first fin of semiconductor material of a first finFET and a second fin of semiconductor material of a second finFET on the substrate, so that a fin height of the first fin is substantially equal to a fin height of the second fin;   forming isolation oxide over the substrate adjacent to the first fin and the second fin, so that the first fin and the second fin extend above the isolation oxide;   forming an etch mask over the first fin, the second fin and the isolation oxide which exposes the isolation oxide adjacent to the first fin and covers the isolation oxide adjacent to the second fin;   removing a portion of the isolation oxide from areas exposed by the etch mask, so that an exposed fin height of the first fin is at least 25 percent greater than an exposed fin height of the second fin; and   forming a first gate of the first finFET over the first fin so as to extend down sidewalls of the first fin substantially to the isolation oxide and forming a second gate of the second finFET over the second fin so as to extend down sidewalls of the second fin substantially to the isolation oxide.   
     
     
         8 . The method of  claim 7 , wherein:
 the first finFET is a driver finFET in an SRAM cell; and   the second finFET is a passgate finFET in the SRAM cell.   
     
     
         9 . The method of  claim 7 , wherein the first fin and the second fin are formed with substantially equal widths. 
     
     
         10 . The method of  claim 7 , wherein the first fin and fins adjacent to the first fin, and the second fin and fins adjacent to the second fin, are formed on substantially equal pitch distances. 
     
     
         11 . The method of  claim 7 , wherein the first gate and the second gate are formed with substantially equal widths. 
     
     
         12 . A method of forming an integrated circuit, comprising the steps of:
 forming a first fin of a semiconductor material of a first finFET and a second fin of the semiconductor material of a second finFET on a substrate comprising the semiconductor material, so that a fin height of the first fin is substantially equal to a fin height of the second fin;   forming an oxide over the substrate adjacent to the first fin and the second fin, so that the first fin and the second fin extend above the oxide;   forming an etch mask over the isolation oxide, the etch mask exposing the first fin and covering the second fin;   removing the semiconductor material from a top of the first fin without removing the semiconductor material from a top of the second fin, so that a fin height of the first fin above the oxide is at least 25 percent less than a fin height of the second fin above the oxide; and   forming a first gate of the first finFET over the first fin so as to extend down sidewalls of the first fin to the oxide and forming a second gate of the second finFET over the second fin so as to extend down sidewalls of the second fin to the oxide.   
     
     
         13 . The method of  claim 12 , wherein:
 the first finFET is a passgate finFET in an SRAM cell; and   the second finFET is a driver finFET in the SRAM cell.   
     
     
         14 . The method of  claim 12 , wherein the first fin and the second fin are formed with substantially equal widths. 
     
     
         15 . The method of  claim 12 , wherein the first fin and fins adjacent to the first fin, and the second fin and fins adjacent to the second fin, are formed on substantially equal pitch distances. 
     
     
         16 . The method of  claim 12 , wherein the first gate and the second gate are formed with substantially equal widths. 
     
     
         17 . The method of  claim 12 , wherein the first gate and gates adjacent to the first gate, and the second gate and gates adjacent to the second gate, are formed on substantially equal pitch distances.