Inventor · disambiguated record
Thomas M. Maffitt
Also filed as: MAFFITT THOMAS M · MAFFITT THOMAS MARTIN
40 granted patents·1 pending application·438 citations·filing 1995–2019
98Inventor score
Top patents by PatentIndex Score
41 records- 0195US10726897B1Trimming MRAM sense amp with offset cancellationIBM·Filed 2019·Granted Jul 28, 2020·17 cites·20 claims
- 0293US9911492B2Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write periodIBM·Filed 2014·Granted Mar 6, 2018·9 cites·13 claims
- 0393US7535783B2Apparatus and method for implementing precise sensing of PCRAM devicesIBM·Filed 2007·Granted May 19, 2009·32 cites·21 claims
- 0493US6255899B1Method and apparatus for increasing interchip communications ratesIBM·Filed 1999·Granted Jul 3, 2001·136 cites·34 claims
- 0592US6437385B1Integrated circuit capacitorIBM·Filed 2000·Granted Aug 20, 2002·62 cites·12 claims
- 0689US9384792B2Offset-cancelling self-reference STT-MRAM sense amplifierGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 5, 2016·12 cites·10 claims
- 0789US8300489B2Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pumpFIFIELD JOHN A·Filed 2010·Granted Oct 30, 2012·13 cites·24 claims
- 0889US7778065B2Method and apparatus for implementing concurrent multiple level sensing operation for resistive memory devicesIBM·Filed 2008·Granted Aug 17, 2010·21 cites·16 claims
- 0986US10535403B2Writing multiple levels in a phase change memoryIBM·Filed 2018·Granted Jan 14, 2020·3 cites·10 claims
- 1085US10658022B1High gain sense amplifier with offset cancellation for magnetoresistive random access memoryIBM·Filed 2019·Granted May 19, 2020·6 cites·20 claims
- 1183US9502107B2Writing multiple levels in a phase change memoryIBM·Filed 2015·Granted Nov 22, 2016·3 cites·9 claims
- 1283US6496037B1Automatic off-chip driver adjustment based on load characteristicsIBM·Filed 2000·Granted Dec 17, 2002·26 cites·18 claims
- 1373US9583192B1Matchline precharge architecture for self-reference matchline sensingGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 28, 2017·3 cites·20 claims
- 1472US7882455B2Circuit and method using distributed phase change elements for across-chip temperature profilingIBM·Filed 2008·Granted Feb 1, 2011·8 cites·19 claims
- 1569US9299431B2Writing multiple levels in a phase change memory using a write/read reference voltage ramping up over a write/read periodIBM·Filed 2015·Granted Mar 29, 2016·1 cites·15 claims
- 1667US10726898B1MRAM sense amplifier with second stage offset cancellationIBM·Filed 2019·Granted Jul 28, 2020·3 cites·20 claims
- 1766US9601200B2TCAM structures with reduced power supply noiseIBM·Filed 2015·Granted Mar 21, 2017·2 cites·20 claims
- 1865US9704575B1Content-addressable memory having multiple reference matchlines to reduce latencyGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 11, 2017·2 cites·16 claims
- 1965US6693843B1Wordline on and off voltage compensation circuit based on the array device threshold voltageINFINEON TECHNOLOGIES AG·Filed 2002·Granted Feb 17, 2004·14 cites·12 claims
- 2064US7660152B2Method and apparatus for implementing self-referencing read operation for PCRAM devicesIBM·Filed 2008·Granted Feb 9, 2010·5 cites·20 claims
- 2162US11152063B2Writing multiple levels in a phase change memoryIBM·Filed 2019·Granted Oct 19, 2021·0 cites·20 claims
- 2262US10998045B2Writing multiple levels in a phase change memoryIBM·Filed 2019·Granted May 4, 2021·0 cites·12 claims
- 2362US10943658B2Writing multiple levels in a phase change memoryIBM·Filed 2019·Granted Mar 9, 2021·0 cites·15 claims
- 2462US10937496B2Writing multiple levels in a phase change memoryIBM·Filed 2019·Granted Mar 2, 2021·0 cites·13 claims
- 2562US10566057B2Writing multiple levels in a phase change memoryIBM·Filed 2019·Granted Feb 18, 2020·0 cites·12 claims
- 2661US10692576B2Writing multiple levels in a phase change memoryIBM·Filed 2019·Granted Jun 23, 2020·0 cites·20 claims
- 2759US10762959B2Writing multiple levels in a phase change memoryIBM·Filed 2018·Granted Sep 1, 2020·0 cites·10 claims
- 2859US8233345B2Phase change memory cycle timer and methodGABRIC JOHN A·Filed 2010·Granted Jul 31, 2012·2 cites·21 claims
- 2958US10424375B2Writing multiple levels in a phase change memoryIBM·Filed 2017·Granted Sep 24, 2019·0 cites·14 claims
- 3058US6580650B2DRAM word line voltage control to insure full cell writeback levelIBM·Filed 2001·Granted Jun 17, 2003·10 cites·28 claims
- 3156US10037802B2Phase change memory with an incrementally ramped write-reference voltage and an incrementally ramped read-reference voltageIBM·Filed 2016·Granted Jul 31, 2018·0 cites·11 claims
- 3256US5995440AOff-chip driver and receiver circuits for multiple voltage level DRAMsIBM·Filed 1998·Granted Nov 30, 1999·15 cites·6 claims
- 3347US8345475B2Non volatile cell and architecture with single bit random access read, program and eraseIBM·Filed 2009·Granted Jan 1, 2013·1 cites·24 claims
- 3445US7057924B2Precharging the write path of an MRAM device for fast write operationIBM·Filed 2004·Granted Jun 6, 2006·4 cites·16 claims
- 3545US6522154B2Oxide tracking voltage referenceIBM·Filed 2001·Granted Feb 18, 2003·3 cites·14 claims
- 3645US6014046AOff chip driver (OCD) with variable drive capability for noise controlIBM·Filed 1997·Granted Jan 11, 2000·8 cites·11 claims
- 3743US6177818B1Complementary depletion switch body stack off-chip driverIBM·Filed 1999·Granted Jan 23, 2001·6 cites·5 claims
- 3841US5682116AOff chip driver having slew rate control and differential voltage protection circuitryIBM·Filed 1995·Granted Oct 28, 1997·6 cites·19 claims
- 3940US8520458B2Phase change memory cycle timer and methodGABRIC JOHN A·Filed 2012·Granted Aug 27, 2013·0 cites·20 claims
- 4038US6369671B1Voltage controlled transmission line with real-time adaptive controlIBM·Filed 1999·Granted Apr 9, 2002·5 cites·14 claims
- 4131US2009129185A1Semiconductor circuits capable of self detecting defectsCASSELS JOHN J·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →