Inventor · disambiguated record
Dhivya Jeganathan
Also filed as: JEGANATHAN DHIVYA
19 granted patents·29 citations·filing 2015–2021
90Inventor score
Files withIBM19
Top patents by PatentIndex Score
19 records- 0190US11086630B1Finish exception handling of an instruction completion tableIBM·Filed 2020·Granted Aug 10, 2021·3 cites·20 claims
- 0288US9985656B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·7 cites·6 claims
- 0384US9985655B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·6 cites·11 claims
- 0484US9639418B2Parity protection of a registerIBM·Filed 2015·Granted May 2, 2017·4 cites·20 claims
- 0582US9921833B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2015·Granted Mar 20, 2018·3 cites·11 claims
- 0677US9959123B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted May 1, 2018·2 cites·7 claims
- 0776US10176038B2Partial ECC mechanism for a byte-write capable registerIBM·Filed 2015·Granted Jan 8, 2019·2 cites·20 claims
- 0867US10719056B2Merging status and control data in a reservation stationIBM·Filed 2016·Granted Jul 21, 2020·1 cites·20 claims
- 0967US9983879B2Operation of a multi-slice processor implementing dynamic switching of instruction issuance orderIBM·Filed 2016·Granted May 29, 2018·1 cites·18 claims
- 1061US11327757B2Processor providing intelligent management of values buffered in overlaid architected and non-architected register filesIBM·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 1157US11775337B2Prioritization of threads in a simultaneous multithreading processor coreIBM·Filed 2021·Granted Oct 3, 2023·0 cites·17 claims
- 1252US9928073B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2016·Granted Mar 27, 2018·0 cites·6 claims
- 1352US9858078B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted Jan 2, 2018·0 cites·13 claims
- 1451US10489253B2On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessorIBM·Filed 2017·Granted Nov 26, 2019·0 cites·20 claims
- 1549US10649779B2Variable latency pipe for interleaving instruction tags in a microprocessorIBM·Filed 2016·Granted May 12, 2020·0 cites·7 claims
- 1647US10613868B2Variable latency pipe for interleaving instruction tags in a microprocessorIBM·Filed 2015·Granted Apr 7, 2020·0 cites·11 claims
- 1746US10031757B2Operation of a multi-slice processor implementing a mechanism to overcome a system hangIBM·Filed 2016·Granted Jul 24, 2018·0 cites·20 claims
- 1846US9766975B2Partial ECC handling for a byte-write capable registerIBM·Filed 2015·Granted Sep 19, 2017·0 cites·20 claims
- 1943US10445100B2Broadcasting messages between execution slices for issued instructions indicating when execution results are readyIBM·Filed 2016·Granted Oct 15, 2019·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →