Inventor · disambiguated record
Oscar Frederick Jones, Jr.
Also filed as: JONES JR OSCAR F · JONES JR OSCAR FREDERICK · JONES OSCAR F · JONES OSCAR F JR
34 granted patents·4 pending applications·940 citations·filing 1976–2014
98Inventor score
Files withUNITED MEMORIES INC16SONY CORP4ENHANCED MEMORY SYSTEMS INC2JONES JR OSCAR FREDERICK2PARRIS MICHAEL C2
Top patents by PatentIndex Score
38 records- 0196USRE44726EData inversion register technique for integrated circuit memory testingPARRIS MICHAEL C·Filed 2011·Granted Jan 21, 2014·19 cites·28 claims
- 0296US5887272AEnhanced DRAM with embedded registersENHANCED MEMORY SYSTEMS INC·Filed 1997·Granted Mar 23, 1999·126 cites·32 claims
- 0396US5699317AEnhanced DRAM with all reads from on-chip cache and all writers to memory arrayRAMTRON INT CORP·Filed 1994·Granted Dec 16, 1997·189 cites·18 claims
- 0495US5721862AEnhanced DRAM with single row SRAM cache for all device read operationsRAMTRON INT CORP·Filed 1995·Granted Feb 24, 1998·117 cites·36 claims
- 0591US6289413B1Cached synchronous DRAM architecture having a mode register programmable cache policyIBM·Filed 1999·Granted Sep 11, 2001·108 cites·19 claims
- 0690US7631233B2Data inversion register technique for integrated circuit memory testingUNITED MEMORIES INC·Filed 2007·Granted Dec 8, 2009·19 cites·15 claims
- 0790US6622198B2Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architectureUNITED MEMORIES INC·Filed 2001·Granted Sep 16, 2003·66 cites·8 claims
- 0887US5379261AMethod and circuit for improved timing and noise margin in a DRAMUNITED MEMORIES INC·Filed 1993·Granted Jan 3, 1995·64 cites·23 claims
- 0983US7002874B1Dual word line mode for DRAMsSONY CORP·Filed 2005·Granted Feb 21, 2006·14 cites·20 claims
- 1080US6788122B2Clock controlled power-down stateUNITED MEMORIES INC·Filed 2003·Granted Sep 7, 2004·22 cites·10 claims
- 1175US6347357B1Enhanced DRAM with embedded registersENHANCED MEMORY SYSTEMS INC·Filed 1998·Granted Feb 12, 2002·23 cites·4 claims
- 1273US6643212B1Simultaneous function dynamic random access memory device techniqueUNITED MEMORIES INC·Filed 2002·Granted Nov 4, 2003·19 cites·26 claims
- 1371US6667927B2Refresh initiated precharge technique for dynamic random access memory arrays using look-ahead refreshUNITED MEMORIES INC·Filed 2002·Granted Dec 23, 2003·15 cites·6 claims
- 1470US8510641B2Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrixJONES JR OSCAR FREDERICK·Filed 2012·Granted Aug 13, 2013·3 cites·5 claims
- 1567US8281219B2Error correction code (ECC) circuit test modePARRIS MICHAEL C·Filed 2007·Granted Oct 2, 2012·6 cites·20 claims
- 1667US7962837B2Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrixUNITED MEMORIES INC·Filed 2007·Granted Jun 14, 2011·4 cites·7 claims
- 1766US4082071AEngine vent vapor filter and method of constructing sameJONES OSCAR F·Filed 1976·Granted Apr 4, 1978·20 cites·4 claims
- 1864US7099234B2Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAMSONY CORP·Filed 2004·Granted Aug 29, 2006·12 cites·25 claims
- 1964US6912168B2Non-contiguous masked refresh for an integrated circuit memorySONY CORP·Filed 2003·Granted Jun 28, 2005·12 cites·20 claims
- 2063US6732305B2Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitryUNITED MEMORIES INC·Filed 2001·Granted May 4, 2004·12 cites·23 claims
- 2160US7370140B2Enhanced DRAM with embedded registersPURPLE MOUNTAIN SERVER LLC·Filed 2001·Granted May 6, 2008·7 cites·25 claims
- 2260US6608797B1Automatic delay technique for early read and write operations in synchronous dynamic random access memoriesUNITED MEMORIES INC·Filed 2002·Granted Aug 19, 2003·10 cites·16 claims
- 2359US7506100B2Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocksUNITED MEMORIES INC·Filed 2005·Granted Mar 17, 2009·3 cites·19 claims
- 2454US8239740B2Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrixJONES JR OSCAR FREDERICK·Filed 2011·Granted Aug 7, 2012·1 cites·2 claims
- 2554US4426821ATriangular faced polyhedrals formed from end interconnected folded sheet trussesMOORE WAYNE T·Filed 1980·Granted Jan 24, 1984·17 cites·6 claims
- 2649US6657461B2System and method for high speed integrated circuit device testing utilizing a lower speed test environmentMOSEL VITELIC INC·Filed 2001·Granted Dec 2, 2003·4 cites·13 claims
- 2748US7586355B2Low skew clock distribution treeUNITED MEMORIES INC·Filed 2007·Granted Sep 8, 2009·1 cites·20 claims
- 2848US6339346B1Low skew signal generation circuitUNITED MEMORIES INC·Filed 2000·Granted Jan 15, 2002·4 cites·24 claims
- 2946US6625078B2Look-ahead refresh for an integrated circuit memoryUNITED MEMORIES INC·Filed 2002·Granted Sep 23, 2003·3 cites·16 claims
- 3045US9246475B2Dual-complementary integrating duty cycle detector with dead band noise rejectionUNITED MEMORIES INC·Filed 2014·Granted Jan 26, 2016·0 cites·24 claims
- 3145US5373470AMethod and circuit for configuring I/O devicesUNITED MEMORIES INC·Filed 1993·Granted Dec 13, 1994·14 cites·13 claims
- 3243US7110306B2Dual access DRAMSONY CORP·Filed 2004·Granted Sep 19, 2006·3 cites·19 claims
- 3343US6728931B2Time data compression technique for high speed integrated circuit memory devicesPROMOS TECHNOLOGIES INC·Filed 2001·Granted Apr 27, 2004·3 cites·56 claims
- 3443US2009122619A1Enhanced DRAM with Embedded RegistersPURPLE MOUNTAIN SERVER LLC·Filed 2008·Application pending·0 cites
- 3543US2006005053A1Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devicesJONES OSCAR F JR·Filed 2004·Application pending·0 cites
- 3642US7583142B1Low skew differential amplifier using tail voltage reference and tail feedbackPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Granted Sep 1, 2009·0 cites·21 claims
- 3742US2009106488A1Static random access memory (sram) compatible, high availability memory array and method employing synchronous dynamic random access memory (dram) in conjunction with a data cache and separate read and write registers and tag blocksUNITED MEMORIES INC·Filed 2008·Application pending·0 cites
- 3832US2006190678A1Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tagBUTLER DOUGLAS B·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →