Static random access memory (sram) compatible, high availability memory array and method employing synchronous dynamic random access memory (dram) in conjunction with a data cache and separate read and write registers and tag blocks

Abstract

A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

1 . An integrated circuit device capable of hiding DRAM refreshes comprising:
 a dynamic random access memory array comprising a plurality of memory subarrays;   a cache for mirroring any one of said plurality of memory subarrays;   a mirrored subarray pointer for indicating which one of said plurality of memory subarrays is currently being mirrored by said cache;   a data read register for maintaining data that has been read from said memory array;   a data write register for maintaining data that has been read from said cache; and   control logic for controlling said dynamic random access memory array, said cache, said mirrored subarray pointer, said data read register and said data write register such that refresh is hidden.   
     
     
         2 . The integrated circuit device of  claim 1  wherein said data maintained in said data read register is subsequently to be written into said cache. 
     
     
         3 . The integrated circuit device of  claim 2  wherein said data maintained in said data read register is written to said cache in a subsequent device clock cycle. 
     
     
         4 . The integrated circuit device of  claim 1  wherein said data maintained in said data write register is subsequently to be written into said memory array. 
     
     
         5 . The integrated circuit device of  claim 4  wherein said data maintained in said data write register is subsequently to be written to said memory array in a subsequent device clock cycle. 
     
     
         6 . The integrated circuit device of  claim 1  wherein said cache comprises dynamic random access memory cells. 
     
     
         7 . The integrated circuit device of  claim 6  wherein said cache comprises a number of memory cells equal to that of each of said plurality of memory subarrays. 
     
     
         8 . The integrated circuit device of  claim 6  further comprising:
 a refresh counter coupled to said memory array and said cache.   
     
     
         9 . The integrated circuit device of  claim 8  wherein said refresh counter is coupled to said memory array and said cache through respective internal array and cache address busses. 
     
     
         10 . The integrated circuit device of  claim 1  further comprising:
 an address control block for receiving addresses supplied externally to said integrated circuit device.   
     
     
         11 . The integrated circuit device of  claim 10  wherein said address control block is coupled to said memory array and said cache through an external address bus. 
     
     
         12 . The integrated circuit device of  claim 11  further comprising:
 an internal array address bus and an internal cache address bus separate from said external address bus.   
     
     
         13 . The integrated circuit device of  claim 12  further comprising:
 a refresh counter coupled to said internal array address bus and said internal cache address bus.   
     
     
         14 . The integrated circuit device of  claim 12  further comprising:
 a write-back counter coupled to said internal array address bus and said internal cache address bus.   
     
     
         15 . The integrated circuit device of  claim 12  further comprising:
 a write tag block and a read tag block for tracking valid data in said cache.   
     
     
         16 . The integrated circuit device of  claim 15  further comprising:
 a write tag address bus coupled to said write tag block; and   a read tag address bus coupled to said read tag block, said write and read tag address busses being coupled to said external address bus.   
     
     
         17 . The integrated circuit device of  claim 14  further comprising:
 write and read tag blocks for tracking valid data in said cache coupled to said write-back counter.   
     
     
         18 . The integrated circuit device of  claim 1  further comprising:
 a data input/output block for receiving data to be written to said device and for outputting data to be read from said device.   
     
     
         19 . The integrated circuit device of  claim 18  further comprising:
 a global data read/write bus coupling said data input/output block to each of said plurality of memory subarrays and said cache.   
     
     
         20 . The integrated circuit device of  claim 18  further comprising:
 a cache read/write bus coupling said data input/output block to said data read and said data write registers.   
     
     
         21 . The integrated circuit device of  claim 1  wherein each of said memory subarrays comprise a like number of memory cells. 
     
     
         22 . The integrated circuit device of  claim 12  further comprising:
 a control logic block coupled to said external address bus for selectively enabling said plurality of memory subarrays to respond to addresses on either of said internal array address bus or said external address bus.   
     
     
         23 . The integrated circuit device of  claim 22  wherein said control logic block is further operative for selectively enabling said cache to respond to addresses on either of said internal cache address bus or said external address bus. 
     
     
         24 . The integrated circuit device of  claim 22  wherein said control logic block is responsive to an externally supplied clock signal. 
     
     
         25 . The integrated circuit device of  claim 22  wherein said control logic block is responsive to an externally supplied write enable. 
     
     
         26 . The integrated circuit device of  claim 22  wherein said control logic block is responsive to an externally supplied chip enable signal. 
     
     
         27 . The integrated circuit device of  claim 14  further comprising:
 a control logic block for supplying an increment signal to said write-back counter.   
     
     
         28 . The integrated circuit device of  claim 27  wherein said control logic is further operative to supply a reset signal to said write-back counter. 
     
     
         29 . The integrated circuit device of  claim 27  wherein said control logic block is coupled to receive an output of said write-back counter. 
     
     
         30 . The integrated circuit device of  claim 8  further comprising:
 a control logic block for supplying an increment signal to said refresh counter.   
     
     
         31 . The integrated circuit device of  claim 30  wherein said control logic is further operative to supply a reset signal to said refresh counter. 
     
     
         32 . The integrated circuit device of  claim 30  wherein said control logic block is coupled to receive an output of said refresh counter. 
     
     
         33 . The integrated circuit device of  claim 15  further comprising:
 a control logic block for supplying a tag enable signal to said write and read tag blocks.   
     
     
         34 . The integrated circuit device of  claim 33  wherein said read tag block is operative to supply a tag read data signal to said control block. 
     
     
         35 . The integrated circuit device of  claim 33  wherein said control logic block is operative to supply a tag write data signal to said write tag block. 
     
     
         36 . The integrated circuit device of  claim 1  wherein refresh operations to said memory array may occur with sufficient frequency to enable device response to a read or write access operation without losing data maintained in said memory array. 
     
     
         37 . The integrated circuit device of  claim 1  wherein any of said plurality of memory subarrays may be written from said cache or refreshed substantially concurrently with any other of said plurality of memory subarrays being read from or written to. 
     
     
         38 . The integrated circuit device of  claim 11  further comprising:
 a previous external address register coupled to said external address bus for storing an external address for at least one cycle.   
     
     
         39 . The integrated circuit device of  claim 38  further comprising:
 a write tag block coupled to said previous external address register.   
     
     
         40 . An integrated circuit device capable of hiding DRAM refreshes comprising:
 a dynamic random access memory array comprising a plurality of memory subarrays;   a cache for mirroring any one of said plurality of memory subarrays;   a mirrored subarray pointer for indicating which one of said plurality of memory subarrays is currently being mirrored by said cache;   a data read register for maintaining data that has been read from said memory array; and   control logic for controlling said dynamic random access memory array, said cache, said mirrored subarray pointer, and said data read register such that refresh is hidden.   
     
     
         41 . The integrated circuit device of  claim 40  wherein said data maintained in said data read register is subsequently to be written into said cache. 
     
     
         42 . The integrated circuit device of  claim 41  wherein said data maintained in said data read register is written to said cache in a subsequent device clock cycle. 
     
     
         43 . The integrated circuit device of  claim 40  wherein said cache comprises dynamic random access memory cells. 
     
     
         44 . The integrated circuit device of  claim 40  wherein said cache comprises a number of memory cells equal to that of each of said plurality of memory subarrays. 
     
     
         45 . The integrated circuit device of  claim 40  further comprising:
 a refresh counter coupled to said memory array and said cache.   
     
     
         46 . The integrated circuit device of  claim 45  wherein said refresh counter is coupled to said memory array and said cache through respective internal array and cache address busses. 
     
     
         47 . The integrated circuit device of  claim 40  further comprising:
 an address control block for receiving addresses supplied externally to said integrated circuit device.   
     
     
         48 . The integrated circuit device of  claim 47  wherein said address control block is coupled to said memory array and said cache through an external address bus. 
     
     
         49 . The integrated circuit device of  claim 48  further comprising:
 an internal array address bus and an internal cache address bus separate from said external address bus.   
     
     
         50 . An integrated circuit device capable of hiding DRAM refreshes comprising:
 a dynamic random access memory array comprising a plurality of memory subarrays;   a cache for mirroring any one of said plurality of memory subarrays;   a mirrored subarray pointer for indicating which one of said plurality of memory subarrays is currently being mirrored by said cache;   a data write register for maintaining data that has been read from said cache; and   control logic for controlling said dynamic random access memory array, said cache, said mirrored subarray pointer, and said data write register such that refresh is hidden.   
     
     
         51 . The integrated circuit device of  claim 50  wherein said data maintained in said data write register is subsequently to be written into said memory array. 
     
     
         52 . The integrated circuit device of  claim 51  wherein said data maintained in said data write register is written to said memory array in a subsequent device clock cycle. 
     
     
         53 . The integrated circuit device of  claim 50  wherein said cache comprises dynamic random access memory cells. 
     
     
         54 . The integrated circuit device of  claim 50  wherein said cache comprises a number of memory cells equal to that of each of said plurality of memory subarrays. 
     
     
         55 . The integrated circuit device of  claim 50  further comprising:
 a refresh counter coupled to said memory array and said cache.   
     
     
         56 . The integrated circuit device of  claim 55  wherein said refresh counter is coupled to said memory array and said cache through respective internal array and cache address busses. 
     
     
         57 . The integrated circuit device of  claim 50  further comprising:
 an address control block for receiving addresses supplied externally to said integrated circuit device.   
     
     
         58 . The integrated circuit device of  claim 57  wherein said address control block is coupled to said memory array and said cache through an external address bus. 
     
     
         59 . The integrated circuit device of  claim 58  further comprising:
 an internal array address bus and an internal cache address bus separate from said external address bus.   
     
     
         60 . An integrated circuit device capable of hiding DRAM refreshes comprising:
 a dynamic random access memory array comprising a plurality of memory subarrays;   a cache for mirroring any one of said plurality of memory subarrays;   a mirrored subarray pointer for indicating which one of said plurality of memory subarrays is currently being mirrored by said cache;   a write tag block;   a read tag block; and   control logic for controlling said dynamic random access memory array, said cache, said mirrored subarray pointer, said write tag block, and said read tag block such that refresh is hidden.   
     
     
         61 . The integrated circuit device of  claim 60  further comprising:
 means for substantially concurrently accessing said write tag block with an external address and said read tag block with an external address.   
     
     
         62 . The integrated circuit device of  claim 60  further comprising:
 means for substantially concurrently accessing said read tag block with an external address and said write tag block with a write-back address.   
     
     
         63 . The integrated circuit device of  claim 60  wherein said cache comprises dynamic random access memory cells. 
     
     
         64 . The integrated circuit device of  claim 63  wherein said cache comprises a number of memory cells equal to that of each of said plurality of memory subarrays. 
     
     
         65 . The integrated circuit device of  claim 63  further comprising:
 a refresh counter coupled to said memory array and said cache.   
     
     
         66 . The integrated circuit device of  claim 65  wherein said refresh counter is coupled to said memory array and said cache through respective internal array and cache address busses. 
     
     
         67 . The integrated circuit device of  claim 60  further comprising:
 an address control block for receiving addresses supplied externally to said integrated circuit device.   
     
     
         68 . The integrated circuit device of  claim 67  wherein said address control block is coupled to said memory array and said cache through an external address bus. 
     
     
         69 . The integrated circuit device of  claim 68  further comprising:
 an internal array address bus and an internal cache address bus separate from said external address bus.   
     
     
         70 . The integrated circuit device of  claim 69  further comprising:
 a refresh counter coupled to said internal array address bus and said internal cache address bus.   
     
     
         71 . The integrated circuit device of  claim 69  further comprising:
 a write-back counter coupled to said internal array address bus and said internal cache address bus.   
     
     
         72 . The integrated circuit device of  claim 68  further comprising:
 a write tag address bus coupled to said write tag block; and   a read tag address bus coupled to said read tag block, said write and read tag address busses being coupled to said external address bus.   
     
     
         73 . An integrated circuit device capable of hiding DRAM refreshes comprising:
 a dynamic random access memory array comprising a plurality of memory subarrays;   a cache for mirroring any one of said plurality of memory subarrays;   a mirrored subarray pointer for indicating which one of said plurality of memory subarrays is currently being mirrored by said cache;   means for indicating if valid data is currently in said cache or a mirrored one of said plurality of memory subarrays; and   control logic for controlling said dynamic random access memory array, said cache, and said mirrored subarray pointer such that refresh is hidden.   
     
     
         74 . The integrated circuit device of  claim 73  wherein said cache comprises dynamic random access memory cells. 
     
     
         75 . The integrated circuit device of  claim 74  wherein said cache comprises a number of memory cells equal to that of each of said plurality of memory subarrays. 
     
     
         76 . The integrated circuit device of  claim 73  further comprising:
 a refresh counter coupled to said memory array and said cache.   
     
     
         77 . The integrated circuit device of  claim 76  wherein said refresh counter is coupled to said memory array and said cache through respective internal array and cache address busses. 
     
     
         78 . The integrated circuit device of  claim 73  further comprising:
 an address control block for receiving addresses supplied externally to said integrated circuit device.   
     
     
         79 . The integrated circuit device of  claim 78  wherein said address control block is coupled to said memory array and said cache through an external address bus. 
     
     
         80 . The integrated circuit device of  claim 79  further comprising:
 an internal array address bus and an internal cache address bus separate from said external address bus.   
     
     
         81 . The integrated circuit device of  claim 80  further comprising:
 a refresh counter coupled to said internal array address bus and said internal cache address bus.   
     
     
         82 . The integrated circuit device of  claim 80  further comprising:
 a write-back counter coupled to said internal array address bus and said internal cache address bus.   
     
     
         83 . The integrated circuit device of  claim 80  wherein said means for indicating if valid data is currently in said cache or a mirrored one of said plurality of memory subarrays comprises:
 a write tag block and a read tag block for tracking valid data in said cache.   
     
     
         84 . The integrated circuit device of  claim 83  further comprising:
 a write tag address bus coupled to said write tag block; and   a read tag address bus coupled to said read tag block, said write and read tag address busses being coupled to said external address bus.   
     
     
         85 . The integrated circuit device of  claim 82  wherein said means for indicating if valid data is currently in said cache or a mirrored one of said plurality of memory subarrays comprises:
 write and read tag blocks for tracking valid data in said cache coupled to said write-back counter.   
     
     
         86 . The integrated circuit device of  claim 73  further comprising:
 a data input/output block for receiving data to be written to said device and for outputting data to be read from said device.   
     
     
         87 . The integrated circuit device of  claim 80  further comprising:
 means for multiplexing addresses on said external address, internal array address bus and internal cache address busses substantially concurrently with a determination as to whether valid data is currently in said cache or a mirrored one of said plurality of memory subarrays.   
     
     
         88 . An integrated circuit device capable of hiding DRAM refreshes comprising:
 a dynamic random access memory array comprising a plurality of memory subarrays;   a cache for mirroring any one of said plurality of memory subarrays;   a mirrored subarray pointer for indicating which one of said plurality of memory subarrays is currently being mirrored by said cache; and   control logic for limiting access to a predetermined number of said plurality of memory subarrays and said cache at a time, and for controlling said dynamic random access memory array, said cache, and said mirrored subarray pointer such that refresh is hidden.   
     
     
         89 . The integrated circuit device of  claim 88  wherein said cache comprises dynamic random access memory cells. 
     
     
         90 . The integrated circuit device of  claim 89  wherein said cache comprises a number of memory cells equal to that of each of said plurality of memory subarrays. 
     
     
         91 . The integrated circuit device of  claim 88  wherein said control logic is operative to limit access to said cache and one of said plurality of memory subarrays at a time. 
     
     
         92 . The integrated circuit device of  claim 88  wherein said control logic is operative to limit access to two of said plurality of memory subarrays at a time.