Inventor · disambiguated record
James S. Blomgren
Also filed as: BLOMGREN JAMES S
117 granted patents·5,632 citations·filing 1991–2016
99Inventor score
Top patents by PatentIndex Score
117 records- 0198US5598546ADual-architecture super-scalar pipelineEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 28, 1997·390 cites·21 claims
- 0297US5477082ABi-planar multi-chip moduleEXPONENTIAL TECHN INC·Filed 1994·Granted Dec 19, 1995·327 cites·13 claims
- 0395US7219326B2Physical realization of dynamic logic using parameterized tile partitioningINTRINSITY INC·Filed 2003·Granted May 15, 2007·198 cites·9 claims
- 0494US5781750ADual-instruction-set architecture CPU with hidden software emulation modeEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 14, 1998·209 cites·20 claims
- 0594US5481684AEmulating operating system calls in an alternate instruction set using a modified code segment descriptorEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 2, 1996·231 cites·6 claims
- 0692US5481693AShared register architecture for a dual-instruction-set CPUEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 2, 1996·153 cites·7 claims
- 0791US5848264ADebug and video queue for multi-processor chipS3 INC·Filed 1996·Granted Dec 8, 1998·204 cites·20 claims
- 0891US5781457AMerge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALUEXPONENTIAL TECHN INC·Filed 1996·Granted Jul 14, 1998·189 cites·16 claims
- 0991US5745913AMulti-processor DRAM controller that prioritizes row-miss requests to stale banksEXPONENTIAL TECHN INC·Filed 1996·Granted Apr 28, 1998·207 cites·19 claims
- 1091US5542059ADual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence orderEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 30, 1996·159 cites·16 claims
- 1190US5732209ASelf-testing multi-processor die with internal compare pointsEXPONENTIAL TECHN INC·Filed 1996·Granted Mar 24, 1998·306 cites·19 claims
- 1289US9600288B1Result bypass cachePOTTER TERENCE M·Filed 2012·Granted Mar 21, 2017·22 cites·25 claims
- 1387US5455909AMicroprocessor with operation capture facilityCHIPS & TECH INC·Filed 1992·Granted Oct 3, 1995·145 cites·5 claims
- 1486US6260131B1Method and apparatus for TLB memory orderingINTRINSITY INC·Filed 1998·Granted Jul 10, 2001·133 cites·20 claims
- 1586US5551001AMaster-slave cache system for instruction and data cache memoriesEXPONENTIAL TECHN INC·Filed 1994·Granted Aug 27, 1996·132 cites·16 claims
- 1685US5440710AEmulation of segment bounds checking using paging with sub-page validityEXPONENTIAL TECHN INC·Filed 1994·Granted Aug 8, 1995·97 cites·25 claims
- 1784US9417843B2Extended multiplyAPPLE INC·Filed 2013·Granted Aug 16, 2016·7 cites·20 claims
- 1884US6066965AMethod and apparatus for a N-nary logic circuit using 1 of 4 signalsEVSX INC·Filed 1998·Granted May 23, 2000·48 cites·16 claims
- 1983US5828578AMicroprocessor with a large cache shared by redundant CPUs for increasing manufacturing yieldS3 INC·Filed 1995·Granted Oct 27, 1998·109 cites·13 claims
- 2082US6898691B2Rearranging data between vector and matrix forms in a SIMD matrix processorINTRINSITY INC·Filed 2002·Granted May 24, 2005·42 cites·13 claims
- 2182US5685009AShared floating-point registers and register port-pairing in a dual-architecture CPUEXPONENTIAL TECHN INC·Filed 1995·Granted Nov 4, 1997·113 cites·19 claims
- 2282US5664159AMethod for emulating multiple debug breakpoints by page partitioning using a single breakpoint registerEXPONENTIAL TECHN INC·Filed 1995·Granted Sep 2, 1997·106 cites·18 claims
- 2382US5608886ABlock-based branch prediction using a target finder array storing target sub-addressesEXPONENTIAL TECHN INC·Filed 1994·Granted Mar 4, 1997·100 cites·21 claims
- 2480US6622240B1Method and apparatus for pre-branch instructionINTRINSITY INC·Filed 2000·Granted Sep 16, 2003·30 cites·32 claims
- 2580US6107835AMethod and apparatus for a logic circuit with constant power consumptionINTRINSITY INC·Filed 1998·Granted Aug 22, 2000·36 cites·20 claims
- 2680US6069497AMethod and apparatus for a N-nary logic circuit using 1 of N signalsEVSX INC·Filed 1998·Granted May 30, 2000·40 cites·24 claims
- 2780US5884057ATemporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processorEXPONENTIAL TECHN INC·Filed 1995·Granted Mar 16, 1999·103 cites·14 claims
- 2879US9652233B2Hint values for use with an operand cacheAPPLE INC·Filed 2013·Granted May 16, 2017·6 cites·20 claims
- 2979US6211456B1Method and apparatus for routing 1 of 4 signalsINTRINSITY INC·Filed 1998·Granted Apr 3, 2001·34 cites·20 claims
- 3078US5687336AStack push/pop tracking and pairing in a pipelined processorEXPONENTIAL TECHN INC·Filed 1996·Granted Nov 11, 1997·84 cites·19 claims
- 3177US6349387B1Dynamic adjustment of the clock rate in logic circuitsINTRINSITY INC·Filed 2000·Granted Feb 19, 2002·17 cites·20 claims
- 3277US6118304AMethod and apparatus for logic synchronizationINTRINSITY INC·Filed 1998·Granted Sep 12, 2000·33 cites·25 claims
- 3377US5634118ASplitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translationEXPONENTIAL TECHN INC·Filed 1995·Granted May 27, 1997·82 cites·20 claims
- 3476US9459869B2Intelligent caching for an operand cacheAPPLE INC·Filed 2013·Granted Oct 4, 2016·4 cites·19 claims
- 3576US9378146B2Operand cache designAPPLE INC·Filed 2013·Granted Jun 28, 2016·4 cites·18 claims
- 3676US6557021B1Rounding anticipator for floating point operationsINTRINSITY INC·Filed 2000·Granted Apr 29, 2003·23 cites·16 claims
- 3776US5652872ATranslator having segment bounds encoding for storage in a TLBEXPONENTIAL TECHN INC·Filed 1995·Granted Jul 29, 1997·81 cites·20 claims
- 3876US5542109AAddress tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuitiesEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 30, 1996·73 cites·10 claims
- 3975US9264066B2Type conversion using floating-point unitAPPLE INC·Filed 2013·Granted Feb 16, 2016·5 cites·14 claims
- 4075US6499044B1Leading zero/one anticipator for floating pointFiled 2000·Granted Dec 24, 2002·31 cites·28 claims
- 4175US6076155AShared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction setsS3 INC·Filed 1998·Granted Jun 13, 2000·73 cites·26 claims
- 4274US6567835B1Method and apparatus for a 5:2 carry-save-adder (CSA)INTRINSITY INC·Filed 1999·Granted May 20, 2003·62 cites·12 claims
- 4373US6275841B11-of-4 multiplierINTRINSITY INC·Filed 1998·Granted Aug 14, 2001·33 cites·24 claims
- 4473US6181596B1Method and apparatus for a RAM circuit having N-Nary output interfaceINTRINSITY INC·Filed 1999·Granted Jan 30, 2001·21 cites·10 claims
- 4572US6956406B2Static storage element for dynamic logicINTRINSITY INC·Filed 2002·Granted Oct 18, 2005·15 cites·18 claims
- 4672US6370632B1Method and apparatus that enforces a regional memory model in hierarchical memory systemsINTRINSITY INC·Filed 1998·Granted Apr 9, 2002·63 cites·9 claims
- 4771US9632785B2Instruction source specificationAPPLE INC·Filed 2016·Granted Apr 25, 2017·1 cites·20 claims
- 4871US6460134B1Method and apparatus for a late pipeline enhanced floating point unitINTRINSITY INC·Filed 1998·Granted Oct 1, 2002·24 cites·9 claims
- 4971US6275838B1Method and apparatus for an enhanced floating point unit with graphics and integer capabilitiesINTRINSITY INC·Filed 1998·Granted Aug 14, 2001·59 cites·12 claims
- 5069US6288589B1Method and apparatus for generating clock signalsINTRINSITY INC·Filed 1998·Granted Sep 11, 2001·29 cites·20 claims
Showing the top 50 of 117 patent records by PatentIndex Score.
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