Assignee
INTRINSITY INC
US·69 granted patents·1,544 citations·filing 1998–2003
Top patents by PatentIndex Score
69 records- 0195US7219326B2Physical realization of dynamic logic using parameterized tile partitioningINTRINSITY INC·Filed 2003·Granted May 15, 2007·198 cites·9 claims
- 0286US6260131B1Method and apparatus for TLB memory orderingINTRINSITY INC·Filed 1998·Granted Jul 10, 2001·133 cites·20 claims
- 0385US6272653B1Method and apparatus for built-in self-test of logic circuitryINTRINSITY INC·Filed 1998·Granted Aug 7, 2001·86 cites·32 claims
- 0482US6898691B2Rearranging data between vector and matrix forms in a SIMD matrix processorINTRINSITY INC·Filed 2002·Granted May 24, 2005·42 cites·13 claims
- 0580US6622240B1Method and apparatus for pre-branch instructionINTRINSITY INC·Filed 2000·Granted Sep 16, 2003·30 cites·32 claims
- 0680US6107835AMethod and apparatus for a logic circuit with constant power consumptionINTRINSITY INC·Filed 1998·Granted Aug 22, 2000·36 cites·20 claims
- 0779US6211456B1Method and apparatus for routing 1 of 4 signalsINTRINSITY INC·Filed 1998·Granted Apr 3, 2001·34 cites·20 claims
- 0878US6457170B1Software system build method and apparatus that supports multiple users in a software development environmentINTRINSITY INC·Filed 1999·Granted Sep 24, 2002·91 cites·9 claims
- 0977US6349387B1Dynamic adjustment of the clock rate in logic circuitsINTRINSITY INC·Filed 2000·Granted Feb 19, 2002·17 cites·20 claims
- 1077US6118304AMethod and apparatus for logic synchronizationINTRINSITY INC·Filed 1998·Granted Sep 12, 2000·33 cites·25 claims
- 1176US6557021B1Rounding anticipator for floating point operationsINTRINSITY INC·Filed 2000·Granted Apr 29, 2003·23 cites·16 claims
- 1274US6567835B1Method and apparatus for a 5:2 carry-save-adder (CSA)INTRINSITY INC·Filed 1999·Granted May 20, 2003·62 cites·12 claims
- 1373US6275841B11-of-4 multiplierINTRINSITY INC·Filed 1998·Granted Aug 14, 2001·33 cites·24 claims
- 1473US6181596B1Method and apparatus for a RAM circuit having N-Nary output interfaceINTRINSITY INC·Filed 1999·Granted Jan 30, 2001·21 cites·10 claims
- 1572US6956406B2Static storage element for dynamic logicINTRINSITY INC·Filed 2002·Granted Oct 18, 2005·15 cites·18 claims
- 1672US6438743B1Method and apparatus for object cache registration and maintenance in a networked software development environmentINTRINSITY INC·Filed 1999·Granted Aug 20, 2002·66 cites·12 claims
- 1772US6370632B1Method and apparatus that enforces a regional memory model in hierarchical memory systemsINTRINSITY INC·Filed 1998·Granted Apr 9, 2002·63 cites·9 claims
- 1871US6460134B1Method and apparatus for a late pipeline enhanced floating point unitINTRINSITY INC·Filed 1998·Granted Oct 1, 2002·24 cites·9 claims
- 1971US6275838B1Method and apparatus for an enhanced floating point unit with graphics and integer capabilitiesINTRINSITY INC·Filed 1998·Granted Aug 14, 2001·59 cites·12 claims
- 2069US6288589B1Method and apparatus for generating clock signalsINTRINSITY INC·Filed 1998·Granted Sep 11, 2001·29 cites·20 claims
- 2168US6367065B1Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluationINTRINSITY INC·Filed 1998·Granted Apr 2, 2002·23 cites·30 claims
- 2265US6301600B1Method and apparatus for dynamic partitionable saturating adder/subtractorINTRINSITY INC·Filed 1998·Granted Oct 9, 2001·46 cites·11 claims
- 2365US6268746B1Method and apparatus for logic synchronizationINTRINSITY INC·Filed 2000·Granted Jul 31, 2001·10 cites·16 claims
- 2464US6728654B2Random number indexing method and apparatus that eliminates software call sequence dependencyINTRINSITY INC·Filed 2001·Granted Apr 27, 2004·11 cites·12 claims
- 2562US7099812B2Grid that tracks the occurrence of a N-dimensional matrix of combinatorial events in a simulation using a linear indexINTRINSITY INC·Filed 2001·Granted Aug 29, 2006·9 cites·11 claims
- 2662US6202194B1Method and apparatus for routing 1 of N signalsINTRINSITY INC·Filed 1998·Granted Mar 13, 2001·20 cites·25 claims
- 2759US6732346B2Generation of route rulesINTRINSITY INC·Filed 2002·Granted May 4, 2004·9 cites·12 claims
- 2858US6745357B2Dynamic logic scan gate method and apparatusINTRINSITY INC·Filed 2001·Granted Jun 1, 2004·8 cites·16 claims
- 2955US6714045B2Static transmission of FAST14 logic 1-of-N signalsINTRINSITY INC·Filed 2002·Granted Mar 30, 2004·6 cites·12 claims
- 3055US6209076B1Method and apparatus for two-stage address generationINTRINSITY INC·Filed 1998·Granted Mar 27, 2001·29 cites·31 claims
- 3154US7346484B2Monitor manager that creates and executes state machine-based monitor instances in a digital simulationINTRINSITY INC·Filed 2002·Granted Mar 18, 2008·4 cites·12 claims
- 3253US6604065B1Multiple-state simulation for non-binary logicINTRINSITY INC·Filed 1999·Granted Aug 5, 2003·27 cites·22 claims
- 3353US6104642AMethod and apparatus for 1 of 4 register file designINTRINSITY INC·Filed 1998·Granted Aug 15, 2000·12 cites·28 claims
- 3452US7299461B2Expansion syntaxINTRINSITY INC·Filed 2003·Granted Nov 20, 2007·2 cites·6 claims
- 3549US6911846B1Method and apparatus for a 1 of N signalINTRINSITY INC·Filed 1998·Granted Jun 28, 2005·11 cites·16 claims
- 3646US6289497B1Method and apparatus for N-NARY hardware description languageINTRINSITY INC·Filed 1998·Granted Sep 11, 2001·10 cites·22 claims
- 3745US6345381B1Method and apparatus for a logic circuit design toolINTRINSITY INC·Filed 1998·Granted Feb 5, 2002·19 cites·35 claims
- 3845US6334183B1Method and apparatus for handling partial register accessesINTRINSITY INC·Filed 1998·Granted Dec 25, 2001·17 cites·36 claims
- 3945US6271683B1Dynamic logic scan gate method and apparatusINTRINSITY INC·Filed 1999·Granted Aug 7, 2001·16 cites·20 claims
- 4042US6404233B1Method and apparatus for logic circuit transition detectionINTRINSITY INC·Filed 1998·Granted Jun 11, 2002·7 cites·10 claims
- 4142US6324239B1Method and apparatus for a 1 of 4 shifterINTRINSITY INC·Filed 1998·Granted Nov 27, 2001·6 cites·12 claims
- 4242US6175847B1Shifting for parallel normalization and rounding technique for floating point arithmetic operationsINTRINSITY INC·Filed 1998·Granted Jan 16, 2001·13 cites·4 claims
- 4341US6233707B1Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clockINTRINSITY INC·Filed 1998·Granted May 15, 2001·12 cites·28 claims
- 4440US7053664B2Null value propagation for FAST14 logicINTRINSITY INC·Filed 2002·Granted May 30, 2006·1 cites·8 claims
- 4540US7031897B1Software modeling of logic signals capable of holding more than two valuesINTRINSITY INC·Filed 1999·Granted Apr 18, 2006·11 cites·15 claims
- 4638US6571378B1Method and apparatus for a N-NARY logic circuit using capacitance isolationINTRINSITY INC·Filed 2000·Granted May 27, 2003·1 cites·15 claims
- 4738US6445213B1Method for calculating dynamic logic block propagation delay targets using time borrowingINTRINSITY INC·Filed 2001·Granted Sep 3, 2002·0 cites·14 claims
- 4837US6594803B1Method and apparatus that reports multiple status events with a single monitorINTRINSITY INC·Filed 1999·Granted Jul 15, 2003·15 cites·30 claims
- 4936US6360315B1Method and apparatus that supports multiple assignment codeINTRINSITY INC·Filed 1999·Granted Mar 19, 2002·7 cites·15 claims
- 5036US6334136B1Dynamic 3-level partial result merge adderINTRINSITY INC·Filed 1998·Granted Dec 25, 2001·8 cites·20 claims
Showing the top 50 of 69 patent records by PatentIndex Score.
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