Inventor · disambiguated record
Ajay Anant Ingle
Also filed as: INGLE AJAY · INGLE AJAY A · INGLE AJAY ANANT
35 granted patents·11 pending applications·74 citations·filing 2005–2022
95Inventor score
Files withQUALCOMM INC18INGLE AJAY ANANT7PLONDKE ERICH JAMES6CODRESCU LUCIAN3KOOB CHRISTOPHER EDWARD3
Top patents by PatentIndex Score
46 records- 0186US8250332B2Partitioned replacement for cache memoryPLONDKE ERICH JAMES·Filed 2009·Granted Aug 21, 2012·16 cites·27 claims
- 0281US8812516B2Determining top N or bottom N data values and positionsINGLE AJAY ANANT·Filed 2011·Granted Aug 19, 2014·7 cites·22 claims
- 0378US8719503B2Configurable cache and method to configure sameKOOB CHRISTOPHER EDWARD·Filed 2012·Granted May 6, 2014·4 cites·20 claims
- 0476US9823928B2FIFO load instructionZENG MAO·Filed 2011·Granted Nov 21, 2017·4 cites·23 claims
- 0574US8266409B2Configurable cache and method to configure sameKOOB CHRISTOPHER EDWARD·Filed 2009·Granted Sep 11, 2012·5 cites·38 claims
- 0673US8601234B2Configurable translation lookaside bufferPLONDKE ERICH JAMES·Filed 2007·Granted Dec 3, 2013·5 cites·29 claims
- 0772US8429378B2System and method to manage a translation lookaside bufferINGLE AJAY ANANT·Filed 2010·Granted Apr 23, 2013·4 cites·29 claims
- 0869US9239799B2Memory management unit directed access to system interfacesINGLE AJAY ANANT·Filed 2008·Granted Jan 19, 2016·4 cites·28 claims
- 0967US9116685B2Table call instruction for frequently called functionsPLONDKE ERICH JAMES·Filed 2011·Granted Aug 25, 2015·2 cites·23 claims
- 1065US8990543B2System and method for generating and using predicates within a single instruction packetCODRESCU LUCIAN·Filed 2008·Granted Mar 24, 2015·3 cites·34 claims
- 1163US9639503B2Vector indirect element vertical addressing mode with horizontal permuteQUALCOMM INC·Filed 2013·Granted May 2, 2017·1 cites·24 claims
- 1263US8356145B2Multi-stage multiplexing operation including combined selection and data alignment or data replicationQUALCOMM INC·Filed 2010·Granted Jan 15, 2013·2 cites·30 claims
- 1362US9342479B2Systems and methods of data extraction in a vector processorFRIDMAN JOSE·Filed 2012·Granted May 17, 2016·2 cites·26 claims
- 1462US7620778B2Low power microprocessor cache memory and method of operationQUALCOMM INC·Filed 2005·Granted Nov 17, 2009·5 cites·19 claims
- 1561US8195916B2Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing modeBASSETT PAUL DOUGLAS·Filed 2009·Granted Jun 5, 2012·3 cites·65 claims
- 1660US11983538B2Load-store unit dual tags and replaysCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted May 14, 2024·0 cites·12 claims
- 1759US8464000B2Systems and methods for cache line replacementsINGLE AJAY ANANT·Filed 2008·Granted Jun 11, 2013·1 cites·20 claims
- 1859US7505342B2Memory bus output driver of a multi-bank memory device and method thereforQUALCOMM INC·Filed 2006·Granted Mar 17, 2009·4 cites·14 claims
- 1958US2014068225A1Configurable translation lookaside bufferQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2057US8943293B2Configurable cache and method to configure sameQUALCOMM INC·Filed 2014·Granted Jan 27, 2015·0 cites·20 claims
- 2156US8868888B2System and method of executing instructions in a multi-stage data processing pipelineINGLE AJAY ANANT·Filed 2007·Granted Oct 21, 2014·1 cites·38 claims
- 2256US8099448B2Arithmetic logic and shifting device for use in a processorAHMED MUHAMMAD·Filed 2005·Granted Jan 17, 2012·1 cites·18 claims
- 2355US8812789B2Systems and methods for cache line replacementQUALCOMM INC·Filed 2013·Granted Aug 19, 2014·0 cites·20 claims
- 2452US8185721B2Dual function adder for computing a hardware prefetch address and an arithmetic operation valueINGLE AJAY ANANT·Filed 2008·Granted May 22, 2012·0 cites·26 claims
- 2550US9639356B2Arbitrary size table lookup and permutes with crossbarQUALCOMM INC·Filed 2013·Granted May 2, 2017·0 cites·20 claims
- 2650US9632781B2Vector register addressing and functions based on a scalar register data valueQUALCOMM INC·Filed 2013·Granted Apr 25, 2017·0 cites·23 claims
- 2749US8260990B2Selective preclusion of a bus access requestCODRESCU LUCIAN·Filed 2007·Granted Sep 4, 2012·0 cites·31 claims
- 2849US2011125987A1Dedicated Arithmetic Decoding InstructionQUALCOMM INC·Filed 2009·Application pending·0 cites
- 2947US9130786B2Device and method for computing a channel estimateQUALCOMM INC·Filed 2013·Granted Sep 8, 2015·0 cites·26 claims
- 3047US8688761B2Arithmetic logic and shifting device for use in a processorAHMED MUHAMMAD·Filed 2011·Granted Apr 1, 2014·0 cites·20 claims
- 3147US2012284488A1Methods and Apparatus for Constant Extension in a ProcessorPLONDKE ERICH JAMES·Filed 2011·Application pending·0 cites
- 3247US2012284489A1Methods and Apparatus for Constant Extension in a ProcessorPLONDKE ERICH JAMES·Filed 2011·Application pending·0 cites
- 3346US9824013B2Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processorsKOOB CHRISTOPHER EDWARD·Filed 2012·Granted Nov 21, 2017·0 cites·20 claims
- 3446US9268571B2Selective coupling of an address line to an element bank of a vector register fileQUALCOMM INC·Filed 2012·Granted Feb 23, 2016·0 cites·33 claims
- 3545US2015052330A1Vector arithmetic reductionQUALCOMM INC·Filed 2013·Application pending·0 cites
- 3645US2014281368A1Cycle sliced vectors and slot execution on a shared datapathQUALCOMM INC·Filed 2013·Application pending·0 cites
- 3744US2014258680A1Parallel dispatch of coprocessor instructions in a multi-thread processorQUALCOMM INC·Filed 2013·Application pending·0 cites
- 3843US10466967B2System and method for piecewise linear approximationQUALCOMM INC·Filed 2016·Granted Nov 5, 2019·0 cites·30 claims
- 3942US10489155B2Mixed-width SIMD operations using even/odd register pairs for wide data elementsQUALCOMM INC·Filed 2015·Granted Nov 26, 2019·0 cites·12 claims
- 4042US2013179642A1Non-Allocating Memory Access with Physical AddressPLONDKE ERICH JAMES·Filed 2012·Application pending·0 cites
- 4141US9678754B2System and method of processing hierarchical very long instruction packetsCODRESCU LUCIAN·Filed 2010·Granted Jun 13, 2017·0 cites·28 claims
- 4241US2013145097A1Selective Access of a Store Buffer Based on Cache StateINGLE AJAY ANANT·Filed 2011·Application pending·0 cites
- 4341US2013080738A1Processor configured to perform transactional memory operationsPLONDKE ERICH J·Filed 2011·Application pending·0 cites
- 4437US8787422B2Dual fixed geometry fast fourier transform (FFT)HOFFMAN MARC M·Filed 2011·Granted Jul 22, 2014·0 cites·17 claims
- 4536US8527804B2Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accessesLIN JENTSUNG KEN·Filed 2010·Granted Sep 3, 2013·0 cites·21 claims
- 4636US2019272175A1Single pack & unpack network and method for variable bit width data formats for computational machinesQUALCOMM INC·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →