Configurable translation lookaside buffer

Abstract

A particular method includes receiving at least one translation lookaside buffer (TLB) configuration indicator. The at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB. The method further includes modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.

What is claimed is: 
     
         1 . A method comprising:
 receiving at least one translation lookaside buffer (TLB) configuration indicator, wherein the at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB; and   modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.   
     
     
         2 . The method of  claim 1 , wherein the at least one TLB configuration indicator received from an operating system. 
     
     
         3 . The method of  claim 1 , wherein the at least one TLB configuration indicator includes data in a configuration register. 
     
     
         4 . The method of  claim 1 , wherein modifying the number of searchable entries includes enabling a portion of the TLB to increase the number of searchable entries. 
     
     
         5 . The method of  claim 4 , further comprising setting an invalid indicator for each of the searchable entries in the portion of the TLB that is enabled, wherein the invalid indicator indicates that each of the searchable entries in the portion of the TLB that is enabled may store invalid data. 
     
     
         6 . The method of  claim 1 , wherein the at least one TLB configuration indicator is used to determine whether the TLB has a first number of available entries or a second number of available entries after the number of searchable entries of the TLB is modified. 
     
     
         7 . The method of  claim 1 , wherein modifying the number of searchable entries of the TLB includes:
 disabling a portion of the TLB to decrease the number of searchable entries.   
     
     
         8 . The method of  claim 7 , further comprising:
 copying data from at least one entry of the portion of the TLB that is disabled to least one other portion of the TLB.   
     
     
         9 . The method of  claim 7 , further comprising powering off the portion of the TLB that is disabled. 
     
     
         10 . A method comprising:
 receiving a translation lookaside buffer (TLB) configuration indicator;   disabling a portion of a TLB in response to the TLB configuration indicator indicating a specific number of TLB entries to be disabled, wherein disabling includes blocking signaling to the disabled portion of the TLB;   supplying power to the disabled portion of the TLB for a period of time; and   powering off the disabled portion of the TLB after the period of time.   
     
     
         11 . The method of  claim 10 , wherein a power logic circuit powers off the disabled portion of the TLB, and wherein disabling further includes deselecting output signals corresponding to TLB entries of the disabled portion of the TLB using a multiplexor (MUX). 
     
     
         12 . The method of  claim 10 , further comprising, after disabling the disabled portion of the TLB, determining a new TLB miss rate associated with the TLB prior to powering off the disabled portion of the TLB, wherein the disabled portion of the TLB is powered oft in response to the new TLB miss rate associated with the TLB. 
     
     
         13 . The method of  claim 10 , further comprising, after powering off the disabled portion of the TLB, comparing the TLB configuration indicator to a current configuration of the TLB, wherein the TLB configuration indicator is based on a requested number of TLB entries associated with a software application, 
     
     
         14 . A memory device comprising:
 a configuration register that includes a translation lookaside buffer (TLB) configuration field including a TLB configuration indicator indicating a specific number of searchable entries to be enabled at a TLB,   wherein the TLB configuration indicator identifies a first setting or a second setting, and wherein when the TLB configuration indicator identifies the first setting, the TLB has a first number of searchable entries and when the TLB configuration indicator identifies the second setting, the TLB has a second number of searchable entries, the second number differing from the first number.   
     
     
         15 . The memory device of  claim 14 , wherein the TLB configuration field is programmable by a processor under software control. 
     
     
         16 . The memory device of  claim 15 , wherein the software control is performed by an operating system. 
     
     
         17 . The memory device of  claim 14 , wherein the TLB configuration field has at least two bits and wherein the TLB configuration indicator is configured to further identify a third setting or a fourth setting, the third setting related to a third number of searchable entries of the TLB and the fourth setting related to a fourth number of searchable entries of the TLB. 
     
     
         18 . A system comprising:
 a memory configured to provide a translation lookaside buffer (TLB) configuration indicator, wherein the TLB configuration indicator indicates a specific number of TLB entries to be enabled or disabled; and   a TLB including a first portion having a first number of TLB entries and a second portion having a second number of TLB entries, wherein the first portion is selectively disabled in response to the TLB configuration indicator, wherein disabling includes blocking signaling to the disabled portion of the TLB, and wherein the first portion is powered off after being disabled.   
     
     
         19 . The system of  claim 18  further comprising a logic element responsive to the memory, the logic element having an output coupled to the TLB, wherein the first portion is selectively disabled in response to the output of the logic element. 
     
     
         20 . The system of  claim 19 , wherein the logic element is further responsive to a memory management unit control signal. 
     
     
         21 . The system of  claim 18 , wherein the first portion includes one half the TLB entries in the TLB. 
     
     
         22 . The system of  claim 18 , wherein the first portion includes a different number of TLB entries than the second portion. 
     
     
         23 . The system of  claim 18 , further comprising a multiplexer responsive to outputs of the TLB, wherein the multiplexer is configured to select output signals corresponding to TLB entries that are enabled in response to the TLB configuration indicator, and further comprising a logic circuit coupled to the TLB, wherein the logic circuit is configured to power off TLB entries that are disabled in response to the TLB configuration indicator. 
     
     
         24 . The system of  claim 18 , wherein a plurality of TLB entries in the TLB are populated by a software program. 
     
     
         25 . The system of  claim 18 , wherein the TLB is incorporated within a processor configured to execute a software application and wherein the software application has a mode of operating that uses a third number of TLB entries, wherein the third number of TLB entries is less than the first number of TLB entries. 
     
     
         26 . A non-transitory computer-readable medium, including program code that, when executed by a processor, causes the processor to:
 receive at least one translation lookaside buffer (TLB) configuration indicator, wherein the at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB; and   modify a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.   
     
     
         27 . A non-transitory computer-readable medium, including program code that, when executed by a processor, causes the processor to:
 receive a translation lookaside buffer (TLB) configuration indicator that indicates a specific number of TLB entries to be disabled;   disable a portion of a TLB in response to the TLB configuration indicator, wherein disabling includes blocking signaling to the disabled portion of the TLB;   cause power to be supplied to the disabled portion of the TLB for a period of time; and   cause the disabled portion of the TLB to power off after the period of time.   
     
     
         28 . An apparatus comprising:
 means for storing translated addresses having a plurality of searchable entries; and   means for storing data that contains a configuration field including a configuration indicator indicating a specific number of searchable entries to be enabled at the means for storing translated addresses,   wherein the configuration indicator identifies a first setting or a second setting and wherein when the configuration indicator identifies the first setting, the means for storing translated addresses has a first number of searchable entries and when the configuration indicator identifies the second setting, the means for storing translated addresses has a second number of searchable entries,the second number differing from the first number, and   wherein the means for storing data is distinct from the means for storing translated addresses.   
     
     
         29 . An apparatus comprising:
 means for storing data, wherein the data contains a translation lookaside buffer (TLB) configuration indicator, wherein the TLB configuration indicator indicates a specific number of TLB entries to be enabled or disabled; and   means for storing translated addresses including a first portion having a first number of TLB entries and a second portion having a second number of TLB entries, wherein the first portion is selectively disabled in response to the TLB configuration indicator, wherein disabling includes blocking signaling to the disabled portion of the TLB, and wherein the first portion is powered off after being disabled.